Async Fifo Design in Verilog/RTL
-> You can follow to the guide in drive word folder here at the 3rd chapter: https://docs.google.com/document/d/15RnzLcnxuXr0uYl9RgYWv258rxSE3SRU/edit?usp=sharing&ouid=100976078104610699838&rtpof=true&sd=true
Sources that I've used to create this article
-> Cliff Cummings's Async. FIFO paper : http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
-> Digital Design and Computer Architecture Second Edition by David Money Harris & Sarah L. Harris : Chapter 5.5 Memory Arrays & starting from page 263
-> Crossing clock domains with an Asynchronous FIFO, an article from zipcpu blog site : https://zipcpu.com/blog/2018/07/06/afifo.html
