Std. Core: Input Arbiter

Name

input_arbiter

Version

v1.0.0

Author

Original version for nf10:

Adam Covington (gcoving_at_stanford.edu)

James Hongyi Zeng (hyzeng_at_stanford.edu)

Modified for NetFPGA-SUME by:

Noa Zilberman

Type

IP core (HW)

Location

lib/hw/std/cores/input_arbiter_v1_0_0/

Interface Types

AXI4-Stream

AXI-Lite

Busses

M_AXIS: Master AXI4-Stream bus, Variable width

S_AXIS_0: Slave AXI4-Stream bus, Variable width

S_AXIS_1: Slave AXI4-Stream bus, Variable width

S_AXIS_2: Slave AXI4-Stream bus, Variable width

S_AXIS_3: Slave AXI4-Stream bus, Variable width

S_AXIS_4: Slave AXI4-Stream bus, Variable width

S_AXI: Slave AXI4-Lite

Parameters

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.

C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.

C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

Register map

This module uses register infrastructure Ver 1.00, please refer to here for more details.

0x0 : ID - Block ID

0x4 : VERSION - Block Version

0x8 : FLIP - Returns the negative value of a written register

0xC : PKTIN - Total number of incoming packets

0x10: PKTOUT - Total number of outgoing packets

0x14: DEBUG - Debug register, returns the written value plus a preconfigured value

Description

The function of this block is to merge a number of input streams into one output stream. All input interfaces share the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved. The input port buffering will be handled in the AXI Converter block.