support for vitis 2023.1

Makefile

@@ -14,7 +14,7 @@ help:
 
 SYSROOT :=
 HOST_ARCH := x86
-DEVICE ?= xilinx_u280_xdma_201920_3
+DEVICE ?= xilinx_u280_gen3x16_xdma_1_202211_1
 INTERFACE ?= 0
 JOBS ?= 8
 XCLBIN_NAME ?= demo_if$(INTERFACE)
@@ -27,20 +27,10 @@ BUILD_DIR := ./build_hw_if$(INTERFACE)
 HOST_BUILD_DIR := ./host/build_sw_if$(INTERFACE)
 BINARY_CONTAINERS = $(BUILD_DIR)/${XCLBIN_NAME}.xclbin
 
-COMMON_REPO = ./
 PWD = $(shell readlink -f .)
-ABS_COMMON_REPO = $(shell readlink -f $(COMMON_REPO))
-
 #Include Libraries
-include $(ABS_COMMON_REPO)/common/includes/opencl/opencl.mk
-include $(ABS_COMMON_REPO)/common/includes/xcl2/xcl2.mk
-CXXFLAGS += $(xcl2_CXXFLAGS)
-LDFLAGS += $(xcl2_LDFLAGS)
-SENDER_HOST_SRCS += $(xcl2_SRCS)
-RECEIVER_HOST_SRCS += $(xcl2_SRCS)
-CXXFLAGS += $(opencl_CXXFLAGS) -Wall -O0 -g -std=gnu++14
-CXXFLAGS +=  -DVITIS_PLATFORM=$(VITIS_PLATFORM)
-LDFLAGS += $(opencl_LDFLAGS)
+CXX = g++
+CXXFLAGS = -g -std=c++17 -I$(XILINX_XRT)/include
 SENDER_HOST_SRCS += host/fileops.cpp
 SENDER_HOST_SRCS += host/ip_to_hex.cpp
 RECEIVER_HOST_SRCS += host/fileops.cpp
@@ -49,15 +39,12 @@ SENDER_HOST_SRCS += host/host_sender_if$(INTERFACE).cpp
 RECEIVER_HOST_SRCS += host/host_receiver_if$(INTERFACE).cpp
 
 # Host compiler global settings
-CXXFLAGS += -fmessage-length=0
-LDFLAGS += -lrt -lstdc++
+LDFLAGS = -L$(XILINX_XRT)/lib -lxrt_coreutil -pthread
 
 ifneq ($(HOST_ARCH), x86)
   LDFLAGS += --sysroot=$(SYSROOT)
 endif
 
-LDFLAGS+= -lOpenCL -luuid -lxrt_core -lxilinxopencl
-
 SENDER_EXECUTABLE = $(HOST_BUILD_DIR)/host_sender_if$(INTERFACE)
 RECEIVER_EXECUTABLE = $(HOST_BUILD_DIR)/host_receiver_if$(INTERFACE)
 CMD_ARGS = $(BUILD_DIR)/${XCLBIN_NAME}.xclbin
@@ -113,13 +100,13 @@ exe: $(SENDER_EXECUTABLE) $(RECEIVER_EXECUTABLE)
 # Building Host
 .PHONY: compile
 compile: $(SENDER_EXECUTABLE)
-$(SENDER_EXECUTABLE): check-xrt $(SENDER_HOST_SRCS) $(HOST_HDRS)
+$(SENDER_EXECUTABLE): check-xrt $(SENDER_HOST_SRCS) 
 	mkdir -p $(HOST_BUILD_DIR) 
-	$(CXX) $(CXXFLAGS) $(SENDER_HOST_SRCS) $(HOST_HDRS) -o '$@' $(LDFLAGS)
+	$(CXX) $(CXXFLAGS) $(SENDER_HOST_SRCS) -o '$@' $(LDFLAGS)
 
 compile: $(RECEIVER_EXECUTABLE)
-$(RECEIVER_EXECUTABLE): check-xrt $(RECEIVER_HOST_SRCS) $(HOST_HDRS)
-	$(CXX) $(CXXFLAGS) $(RECEIVER_HOST_SRCS) $(HOST_HDRS) -o '$@' $(LDFLAGS)
+$(RECEIVER_EXECUTABLE): check-xrt $(RECEIVER_HOST_SRCS)
+	$(CXX) $(CXXFLAGS) $(RECEIVER_HOST_SRCS) -o '$@' $(LDFLAGS)
 
 
 check-devices:

README.md

@@ -1,16 +1,16 @@
 # UDP Encryption and Decryption Example Using 2 Network Attached Alveo U280s
 
-UDP encrypt and decrypt example with pre-built network layer and cmac kernels. Note: You will use Vitis 2021.2 to build the bitstream in this tutorial. To use an older version, switch to the branch with the version number that you want to use. 
+UDP encrypt and decrypt example with pre-built network layer and cmac kernels. Note: You will use Vitis 2023.1 to build the bitstream in this tutorial. To use an older version, switch to the branch with the version number that you want to use. 
 
 ## Introduction
 
 In this example, we use Xilinx XUP UDP stack [1] and CMAC kernels as pre-built binary object files (.xo files), and link custom user logic to demonstrate sending and receiving UDP packets between two U280 FPGA accelerator cards. The user logic part has both encryption and decryption kernels implemented using AES-128 block cipher. The AES code used in this example was taken from [2]. OpenCL host applications have also been provided for both sender and receiver. The host code is based on the InAccel runtime [3] and the TCP example in [4]. The sender side host executable is used to read a specific number of packets from a text file. The user can use an AXI-Lite control signal connected to the user logic to either encrypt or directly pass these packets over the network layer and cmac to the receiving host. On the receiver side, the user can read the incoming UDP packets as raw data, or decrypt them.   
 
 ## Pre-requisites
 
-- A build machine with Vitis 2021.2. If you do not have such machine, we can provide you with access to one. [This document](https://github.com/OCT-FPGA/OCT-Tutorials/blob/master/nercsetup/nerc-vm-guide.md) will guide you on how to sign up and obtain access to our build machine.
+- A build machine with Vitis 2023.1. If you do not have such machine, we can provide you with access to one. [This document](https://github.com/OCT-FPGA/OCT-Tutorials/blob/master/nercsetup/nerc-vm-guide.md) will guide you on how to sign up and obtain access to our build machine.
 
-- A Cloudlab experiment should be created with two nodes. Instructions are given [here](https://github.com/OCT-FPGA/oct-tutorials/tree/master/cloudlab-setup). Note that you don't need to set up the experiment until you finish bitstream generation. The Cloudlab experiment is only needed for the targeting workflow. This workflow has been tested and verified using Xilinx RunTime (XRT) version 2021.1. Other versions may also support, but not tested. So, you may select the Cloudlab profile ```fpga-post-boot``` with any of these tool versions, and two compute nodes when creating the experiment.  
+- A Cloudlab experiment should be created with two nodes. Instructions are given [here](https://github.com/OCT-FPGA/oct-tutorials/tree/master/cloudlab-setup). Note that you don't need to set up the experiment until you finish bitstream generation. The Cloudlab experiment is only needed for the targeting workflow. This workflow has been tested and verified using Xilinx RunTime (XRT) version 2023.1. Other versions may also support, but not tested. So, you may select the Cloudlab profile ```oct-u280``` with any of these tool versions, and two compute nodes when creating the experiment.  
 
 ## Architecture
 
@@ -32,7 +32,7 @@ First, you should clone the repository using
 To configure the environment to run Vitis commands, run the following shell commands.
 
 ```bash
-source /tools/Xilinx/Vitis/2021.1/settings64.sh
+source /tools/Xilinx/Vitis/2023.1/settings64.sh
 source /opt/xilinx/xrt/setup.sh
 ```
 
@@ -157,7 +157,7 @@ Example - Send 1 UDP packet with encryption enabled on interface 1 only
 ## References
 [1] XUP Vitis Network Example (VNx) https://github.com/Xilinx/xup_vitis_network_example
 
-[2] An HLS Implementation of the Advanced Encryption Standard (AES) http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ToolsXilinxLabsRTLHLSAES
+[2] AES Implementations https://github.com/hplp/AES_implementations
 
 [3] InAccel runtime https://github.com/inaccel/runtime/tree/Xilinx-MP/src/inaccel
 

host/fileops.cpp

@@ -1,27 +1,6 @@
 #include "fileops.h"
 #include <fstream>
 
-int load_file_to_memory(const char *filename, char **result){ 
-	int size = 0;
-  	FILE *f = fopen(filename, "rb");
-  	if (f == NULL){ 
-		*result = NULL;
-    		return -1; // -1 means file opening fail 
-	} 
-	fseek(f, 0, SEEK_END);
-  	size = ftell(f);
-  	fseek(f, 0, SEEK_SET);
-  	*result = (char *)malloc(size+1);
-	if (size != fread(*result, sizeof(char), size, f)){ 
-		free(*result);
-		return -2; // -2 means file reading fail
-	} 
-	fclose(f);
-	(*result)[size] = 0;
-	return size;
-}
-
-
 char *readFile(const char *fileName){
 	FILE *file = fopen(fileName, "r");
 	char *code;
@@ -39,3 +18,4 @@ char *readFile(const char *fileName){
 	code[n] = '\0';        
     	return code;
 }
+