PandABlocks · tomtrafford · Mar 14, 2024 · Jan 26, 2024 · Jan 26, 2024 · Jan 26, 2024
diff --git a/CONFIG.example b/CONFIG.example
@@ -1,23 +1,23 @@
 # Example configuration file for building PandA firmware, and for simulation
 #
 # Copy this file to a file named CONFIG and edit as appropriate.  Lines that are
-# commented out can be left as they are, the default value is show.  Uncommented
+# commented out can be left as they are, the default value is shown.  Uncommented
 # lines must be assigned values.
 
 # Default build location.  Default is to build in build subdirectory.
 BUILD_DIR = /build
 
 # Development Tool Version
-VIVADO_VER = 2022.2
+# VIVADO_VER = 2023.2
 
 # Definitions needed for FPGA build
 export VIVADO = /scratch/Xilinx/Vivado/\$(VIVADO_VER)/settings64.sh
 # Path to external IP repository (if required)
-export EXT_IP_REPO = /scratch/Xilinx/XAPP589/PICXO_FRACXO_v32_2
+export EXT_IP_REPO = /scratch/Xilinx/XAPP589/PICXO_FRACXO_v40_rev6
 
 
 # Specifiy licence server, if required
-# export LM_LICENCE_FILE =
+# export LM_LICENSE_FILE =
 
 # Location of rootfs builder.  This needs to be at least version 1.13 and can be
 # downloaded from https://github.com/araneidae/rootfs
@@ -28,17 +28,17 @@ export TAR_FILES = /tar-files
 
 # Path to root filesystem
 PANDA_ROOTFS = /repos/PandABlocks-rootfs
-MAKE_ZPKG = $(PANDA_ROOTFS)/make-zpkg
+# MAKE_ZPKG = $(PANDA_ROOTFS)/make-zpkg
 
 # Python interpreter for running scripts
 #
-PYTHON = python3
+# PYTHON = python3
 
 # Sphinx build for documentation.
-SPHINX_BUILD = sphinx-build
+# SPHINX_BUILD = sphinx-build
 
 # List of default targets to build when running make
-DEFAULT_TARGETS = zpkg
+# DEFAULT_TARGETS = zpkg
 
 # FPGA Application Name
 APP_NAME = PandABox-fmc_lback-sfp_lback

diff --git a/Makefile b/Makefile
@@ -7,7 +7,6 @@ SHELL = /bin/bash
 
 # The following symbols MUST be defined in the CONFIG file before being used.
 PANDA_ROOTFS = $(error Define PANDA_ROOTFS in CONFIG file)
-ISE = $(error Define ISE in CONFIG file)
 VIVADO = $(error Define VIVADO in CONFIG file)
 APP_NAME = $(error Define APP_NAME in CONFIG file)
 
@@ -18,7 +17,7 @@ MAKE_ZPKG = $(PANDA_ROOTFS)/make-zpkg
 MAKE_GITHUB_RELEASE = $(PANDA_ROOTFS)/make-github-release.py
 
 BUILD_DIR = $(TOP)/build
-VIVADO_VER = 2022.2
+VIVADO_VER = 2023.2
 DEFAULT_TARGETS = zpkg
 
 
@@ -30,7 +29,6 @@ include CONFIG
 # Now we've loaded the CONFIG compute all the appropriate destinations
 TGT_BUILD_DIR = $(BUILD_DIR)/targets/$(TARGET)
 TEST_DIR = $(TGT_BUILD_DIR)/tests
-#IP_DIR = $(TGT_BUILD_DIR)/ip_repo
 APP_BUILD_DIR = $(BUILD_DIR)/apps/$(APP_NAME)
 AUTOGEN_BUILD_DIR = $(APP_BUILD_DIR)/autogen
 FPGA_BUILD_DIR = $(APP_BUILD_DIR)/FPGA
@@ -45,9 +43,8 @@ TARGET_DIR = $(TOP)/targets/$(TARGET)
 PS_PROJ = $(TGT_BUILD_DIR)/panda_ps/panda_ps.xpr
 IP_PROJ = $(TGT_BUILD_DIR)/ip_repo/managed_ip_project/managed_ip_project.xpr
 TOP_PROJ = $(FPGA_BUILD_DIR)/panda_top/carrier_fpga_top.xpr
-TOP_MODE ?= batch
-TEST_MODE ?= gui
-DEP_MODE ?= batch
+VIVADO_MODE ?= batch
+XSIM_MODE ?= gui
 
 # Store the git hash in top-level build directory 
 VER = $(BUILD_DIR)/VERSION
@@ -202,8 +199,8 @@ run_sim_%: $(TOP)/common/fpga.make
 	mkdir -p $(FPGA_BUILD_DIR)
 	$(MAKE) -C $(FPGA_BUILD_DIR) -f $< VIVADO_VER=$(VIVADO_VER) \
         TOP=$(TOP) TARGET_DIR=$(TARGET_DIR) APP_BUILD_DIR=$(APP_BUILD_DIR) \
-        TGT_BUILD_DIR=$(TGT_BUILD_DIR) TEST_MODE=$(TEST_MODE) \
-        DEP_MODE=$(DEP_MODE) $@
+        TGT_BUILD_DIR=$(TGT_BUILD_DIR) XSIM_MODE=$(XSIM_MODE) \
+        $@
 
 
 # ------------------------------------------------------------------------------
@@ -271,7 +268,7 @@ else
 	@echo building FPGA
 	$(MAKE) -C $(FPGA_BUILD_DIR) -f $< VIVADO_VER=$(VIVADO_VER) \
         TOP=$(TOP) TARGET_DIR=$(TARGET_DIR) APP_BUILD_DIR=$(APP_BUILD_DIR) \
-        TGT_BUILD_DIR=$(TGT_BUILD_DIR) TOP_MODE=$(TOP_MODE) DEP_MODE=$(DEP_MODE) \
+        TGT_BUILD_DIR=$(TGT_BUILD_DIR) VIVADO_MODE=$(VIVADO_MODE) \
         VER=$(VER) TARGET=$(TARGET) GIT_VERSION=$(GIT_VERSION) \
         ZIP_BUILD_DIR=$(BUILD_DIR) $@
 endif
@@ -281,26 +278,21 @@ endif
 # Targets to launch and edit vivado projects in interactive mode
 # Targets : edit_ps_bd ; edit_ips ; carrier-fpga_gui
 
-edit_ps_bd: DEP_MODE=gui 
-ifeq ($(wildcard $(PS_PROJ)), )
-  edit_ps_bd: ps_core
-else
-  edit_ps_bd : 
+edit_ps_bd: ps_core 
 	cd $(TGT_BUILD_DIR)/panda_ps; \
-	. $(VIVADO) && vivado -mode $(DEP_MODE) $(PS_PROJ)
-endif
+	. $(VIVADO) && vivado -mode gui $(PS_PROJ)
 
 edit_ips: carrier_ip
 	cd $(TGT_BUILD_DIR)/ip_repo &&  \
 	. $(VIVADO) && vivado -mode gui $(IP_PROJ)
 
-carrier-fpga_gui: TOP_MODE=gui 
+carrier-fpga_gui: VIVADO_MODE=gui 
 ifeq ($(wildcard $(TOP_PROJ)), )
   carrier-fpga_gui: carrier_fpga
 else
   carrier-fpga_gui : 
 	cd $(FPGA_BUILD_DIR); \
-	. $(VIVADO) && vivado -mode $(TOP_MODE) $(TOP_PROJ)
+	. $(VIVADO) && vivado -mode $(VIVADO_MODE) $(TOP_PROJ)
 endif
 
 .PHONY: edit_ps_bd edit_ips carrier-fpga_gui

diff --git a/common/fpga.make b/common/fpga.make
@@ -7,12 +7,13 @@
 # builds.  These releases are downloaded (as .tar.gz files) from:
 #      https://github.com/Xilinx/u-boot-xlnx
 #      https://github.com/Xilinx/linux-xlnx
+#      https://github.com/Xilinx/arm-trusted-firmware
 # Note: if these files have been downloaded through the releases directory then
 # they need to be renamed with the appropriate {u-boot,linux}-xlnx- prefix so
 # that the file name and contents match.
-MD5_SUM_device-tree-xlnx-xilinx_v2022.2 = 7885c6f69509e425a1800eed326ffee8
-MD5_SUM_u-boot-xlnx-xilinx-v2022.2 = a9e54fff739d5702465c786b5420d31e
-MD5_SUM_arm-trusted-firmware-xilinx-v2022.2 = a47d32e92fed413599093f6d82bf3e0c
+MD5_SUM_device-tree-xlnx-xilinx_v2023.2 = 7789e54fe26457b44354d3de28b21987
+MD5_SUM_u-boot-xlnx-xilinx-v2023.2 = 135d51a81aadaed096a667e41db6e110
+MD5_SUM_arm-trusted-firmware-xilinx-v2023.2 = 812e16408046699ff5fe09f847f4a168
 # The dtc source is obtained from https://git.kernel.org/pub/scm/utils/dtc/dtc.git
 MD5_SUM_dtc-1.7.0 = f8b4469ad89f4b882091895ec60dde6b
 
@@ -143,9 +144,9 @@ $(IP_DIR)/%/IP_DONE : $(TOP)/ip_defs/%.tcl $(IP_BUILD_SCR) | $(IP_PROJ)
 	touch $@
 
 $(PS_CORE) : $(PS_BUILD_SCR) $(PS_CONFIG_SCR) $(TGT_INCL_SCR)
-	$(RUNVIVADO) -mode $(DEP_MODE) -source $< \
+	$(RUNVIVADO) -mode batch -source $< \
 	  -log $(TGT_BUILD_DIR)/build_ps.log -nojournal \
-	  -tclargs $(TOP) $(TARGET_DIR) $(PS_DIR) $@ $(DEP_MODE)
+	  -tclargs $(TOP) $(TARGET_DIR) $(PS_DIR) $@
 
 CARRIER_FPGA_DEPS += $(TOP_BUILD_SCR)
 CARRIER_FPGA_DEPS += $(APP_IP_DEPS)
@@ -154,23 +155,23 @@ CARRIER_FPGA_DEPS += $(TGT_INCL_SCR)
 CARRIER_FPGA_DEPS += $(VER)
 
 $(CARRIER_FPGA_BIT) : $(CARRIER_FPGA_DEPS)
-	$(RUNVIVADO) -mode $(TOP_MODE) -source $< \
+	$(RUNVIVADO) -mode $(VIVADO_MODE) -source $< \
 	  -log $(BUILD_DIR)/build_top.log -nojournal \
 	  -tclargs $(TOP) \
 	  -tclargs $(TARGET_DIR) \
 	  -tclargs $(BUILD_DIR) \
 	  -tclargs $(AUTOGEN) \
 	  -tclargs $(IP_DIR) \
 	  -tclargs $(PS_CORE) \
-	  -tclargs $(TOP_MODE) \
+	  -tclargs $(VIVADO_MODE) \
 	  -tclargs $(PLATFORM)
 
 run_sim_%: $(TOP)/tests/sim/%
-	$(RUNVIVADO) -mode $(TEST_MODE) -source $</bench/$*_tb_compile.tcl \
+	$(RUNVIVADO) -mode $(XSIM_MODE) -source $</bench/$*_tb_compile.tcl \
 	  -log $(BUILD_DIR)/test_build_top.log -nojournal \
 	  -tclargs $(TOP) \
 	  -tclargs $(BUILD_DIR) \
-	  -tclargs $(TEST_MODE)
+	  -tclargs $(XSIM_MODE)
 
 $(FPGA_BIN_FILE): $(CARRIER_FPGA_BIT)
 	echo -e "all:\n{\n    $(CARRIER_FPGA_BIT)\n}\n" > bs.bif

diff --git a/common/python/generate_hdl_timing.py b/common/python/generate_hdl_timing.py
@@ -50,7 +50,9 @@ def add_line(self, values):
             else:
                 # Lut Function values were given in hex, they need to be
                 # converted to an int, for the testbench to pass
-                v = str(int(v, 0))
+                # Use bitmask operator to convert to 32-bit unsigned
+                # as work-around for bug with $fscanf in Vivado2023.2
+                v = str(int(v, 0) & 0xFFFFFFFF)
 
             self.lengths[k] = max(self.lengths[k], len(v))
             self.values[k] = v
@@ -208,11 +210,11 @@ def generate_timing_test(self, block, timing_ini, section, i):
             headerslength=headerslength,
         )
         if block.type == "pcap":
-            self.expand_template("pcap_hdl_timing.v.jinja2", context,
-                                 timing_dir, "hdl_timing.v")
+            self.expand_template("pcap_hdl_timing.sv.jinja2", context,
+                                 timing_dir, "hdl_timing.sv")
         else:
-            self.expand_template("hdl_timing.v.jinja2", context, timing_dir,
-                                 "hdl_timing.v")
+            self.expand_template("hdl_timing.sv.jinja2", context, timing_dir,
+                                 "hdl_timing.sv")
 
     # A script should be generated for each module for running the tests in
     # vivado. regression_tests.tcl searches through hdl_timing and finds every

diff --git a/common/scripts/build_ps.tcl b/common/scripts/build_ps.tcl
@@ -13,9 +13,6 @@ set BUILD_DIR [lindex $argv 2]
 # Output file
 set OUTPUT_FILE [lindex $argv 3]
 
-# Vivado run mode - gui or batch mode
-set MODE [lindex $argv 4]
-
 source $TARGET_DIR/target_incl.tcl
 
 # Create project
@@ -34,9 +31,6 @@ set_property "target_language" "VHDL" $obj
 # (THIS is exported from Vivado design tool)
 source $TARGET_DIR/bd/panda_ps.tcl
 
-# Exit script here if gui mode - i.e. if running 'make edit_ps_bd'
-if {[string match "gui" [string tolower $MODE]]} { return }
-
 # Generate the wrapper
 set design_name [get_bd_designs]
 make_wrapper -files [get_files $design_name.bd] -top -import

diff --git a/common/templates/hdl_timing.v.jinja2 → common/templates/hdl_timing.sv.jinja2 b/common/templates/hdl_timing.v.jinja2 → common/templates/hdl_timing.sv.jinja2
diff --git a/common/templates/module.tcl.jinja2 b/common/templates/module.tcl.jinja2
@@ -22,7 +22,7 @@ read_ip $TGT_BUILD_DIR/ip_repo/{{ ip }}/{{ ip }}.xci
 
 add_files -fileset sim_1 -norecurse \
 {% for i in range(number) %}
-    $BUILD_DIR/hdl_timing/{{block.entity}}/timing{{'%03d'% loop.index|int}}/hdl_timing.v \
+    $BUILD_DIR/hdl_timing/{{block.entity}}/timing{{'%03d'% loop.index|int}}/hdl_timing.sv \
     $BUILD_DIR/hdl_timing/{{block.entity}}/timing{{'%03d'% loop.index|int}}/{{
     loop.index}}{{block.entity}}expected.csv \
 {% endfor %}

diff --git a/common/templates/pcap_hdl_timing.v.jinja2 → common/templates/pcap_hdl_timing.sv.jinja2 b/common/templates/pcap_hdl_timing.v.jinja2 → common/templates/pcap_hdl_timing.sv.jinja2
diff --git a/modules/us_system/us_system.block.ini b/modules/us_system/us_system.block.ini
@@ -6,31 +6,31 @@ extension:
 [TEMP_PS]
 description: On-board CPU temperature
 type: read scalar
-extension: in_temp0_ps_temp
+extension: in_temp7
 scale: 0.001
 offset: 0
 units: deg
 
 [TEMP_PL]
 description: On-board FPGA temperature
 type: read scalar
-extension: in_temp2_pl_temp
+extension: in_temp20
 scale: 0.001
 offset: 0
 units: deg
 
 [VCCINT1]
 type: read scalar
 description: On-board voltage sensor 1
-extension: in_voltage2_vccint
+extension: in_voltage2
 scale: 0.001
 offset: 0
 units: V
 
 [VCCINT2]
 type: read scalar
 description: On-board voltage sensor 2
-extension: in_voltage18_vccint
+extension: in_voltage18
 scale: 0.001
 offset: 0
 units: V

diff --git a/targets/PandABox/bd/panda_ps.tcl b/targets/PandABox/bd/panda_ps.tcl
@@ -20,12 +20,18 @@ set script_folder [_tcl::get_script_folder]
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2022.2
+set scripts_vivado_version 2023.2
 set current_vivado_version [version -short]
 
 if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
    puts ""
-   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+   if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+   } else {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   }
 
    return 1
 }
@@ -44,7 +50,6 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 set list_projs [get_projects -quiet]
 if { $list_projs eq "" } {
    create_project project_1 myproj -part xc7z030sbg485-1
-   set_property BOARD_PART em.avnet.com:picozed_7030:part0:1.0 [current_project]
 }
 
 
@@ -227,7 +232,6 @@ proc create_root_design { parentCell } {
    CONFIG.NUM_READ_THREADS {1} \
    CONFIG.NUM_WRITE_OUTSTANDING {8} \
    CONFIG.NUM_WRITE_THREADS {1} \
-   CONFIG.PHASE {0.000} \
    CONFIG.PROTOCOL {AXI3} \
    CONFIG.READ_WRITE_MODE {WRITE_ONLY} \
    CONFIG.RUSER_BITS_PER_BYTE {0} \
@@ -260,7 +264,6 @@ proc create_root_design { parentCell } {
    CONFIG.NUM_READ_THREADS {1} \
    CONFIG.NUM_WRITE_OUTSTANDING {8} \
    CONFIG.NUM_WRITE_THREADS {1} \
-   CONFIG.PHASE {0.000} \
    CONFIG.PROTOCOL {AXI4} \
    CONFIG.READ_WRITE_MODE {READ_ONLY} \
    CONFIG.RUSER_BITS_PER_BYTE {0} \
@@ -906,13 +909,13 @@ proc create_root_design { parentCell } {
   connect_bd_intf_net -intf_net register_interface_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins register_interface/M00_AXI]
 
   # Create port connections
-  connect_bd_net -net ACLK_1 [get_bd_ports PL_CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins read_dma_interface/ACLK] [get_bd_pins read_dma_interface/M00_ACLK] [get_bd_pins read_dma_interface/S00_ACLK] [get_bd_pins register_interface/ACLK] [get_bd_pins register_interface/M00_ACLK] [get_bd_pins register_interface/S00_ACLK] [get_bd_pins write_dma_converter/s_axi_aclk]
+  connect_bd_net -net ACLK_1 [get_bd_ports PL_CLK] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins read_dma_interface/ACLK] [get_bd_pins read_dma_interface/S00_ACLK] [get_bd_pins read_dma_interface/M00_ACLK] [get_bd_pins register_interface/ACLK] [get_bd_pins register_interface/S00_ACLK] [get_bd_pins register_interface/M00_ACLK] [get_bd_pins write_dma_converter/s_axi_aclk]
   connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins processing_system7_0/IRQ_F2P]
   connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins read_dma_interface/ARESETN] [get_bd_pins register_interface/ARESETN] [get_bd_pins write_dma_converter/s_axi_aresetn]
-  connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports FCLK_RESET0_N] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins read_dma_interface/M00_ARESETN] [get_bd_pins read_dma_interface/S00_ARESETN] [get_bd_pins register_interface/M00_ARESETN] [get_bd_pins register_interface/S00_ARESETN]
-  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0]
-  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1]
-  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+  connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_ports FCLK_RESET0_N] [get_bd_pins read_dma_interface/S00_ARESETN] [get_bd_pins read_dma_interface/M00_ARESETN] [get_bd_pins register_interface/S00_ARESETN] [get_bd_pins register_interface/M00_ARESETN]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_ports FCLK_CLK0]
+  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_ports FCLK_CLK1]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins proc_sys_reset_0/ext_reset_in]
 
   # Create address segments
   assign_bd_address -offset 0x43C00000 -range 0x00020000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M00_AXI/Reg] -force