Merge pull request #1225 from alexhornburg-xlnx/feature/pyxsi_link_poc

Feature/pyxsi link poc

docker/finn_entrypoint.sh

@@ -118,6 +118,7 @@ else
     cd $OLDPWD
   fi
   export PYTHONPATH=$PYTHONPATH:${FINN_ROOT}/deps/pyxsi:${FINN_ROOT}/deps/pyxsi/py
+  export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/lib/x86_64-linux-gnu/:${XILINX_VIVADO}/lib/lnx64.o
 fi
 
 if [ -f "$HLS_PATH/settings64.sh" ];then

fetch-repos.sh

@@ -39,7 +39,7 @@ XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e"
 RFSOC4x2_BDF_COMMIT="13fb6f6c02c7dfd7e4b336b18b959ad5115db696"
 KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79"
 EXP_BOARD_FILES_MD5="226ca927a16ea4ce579f1332675e9e9a"
-PYXSI_COMMIT="dc074bc1b3ecc2ab884531565d1aca6aa33ea5b9"
+PYXSI_COMMIT="8c5abd8546bfc6e31292a52b5374116381239651"
 
 QONNX_URL="https://github.com/fastmachinelearning/qonnx.git"
 FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git"

src/finn/core/rtlsim_exec.py

@@ -46,7 +46,7 @@
 except ModuleNotFoundError:
     PyVerilator = None
 
-import finn.util.pyxsi_rpcclient as pyxsi_rpcclient
+import pyxsi_utils
 
 
 def prep_rtlsim_io_dict(model, execution_context):
@@ -164,9 +164,7 @@ def rtlsim_exec_cppxsi(model, execution_context, dummy_data_mode=False, postproc
             all_verilog_srcs = f.read().split()
         single_src_dir = make_build_dir("rtlsim_" + top_module_name + "_")
 
-        rtlsim_so = pyxsi_rpcclient.compile_sim_obj(
-            top_module_name, all_verilog_srcs, single_src_dir
-        )
+        rtlsim_so = pyxsi_utils.compile_sim_obj(top_module_name, all_verilog_srcs, single_src_dir)
         # save generated lib filename in attribute
         model.set_metadata_prop("rtlsim_so", rtlsim_so[0] + "/" + rtlsim_so[1])
         sim_base, sim_rel = rtlsim_so
@@ -294,26 +292,24 @@ def rtlsim_exec_pyxsi(model, execution_context, pre_hook=None, post_hook=None):
         top_module_name = top_module_file_name.strip(".v")
         single_src_dir = make_build_dir("rtlsim_" + top_module_name + "_")
 
-        rtlsim_so = pyxsi_rpcclient.compile_sim_obj(
-            top_module_name, all_verilog_srcs, single_src_dir
-        )
+        rtlsim_so = pyxsi_utils.compile_sim_obj(top_module_name, all_verilog_srcs, single_src_dir)
         # save generated lib filename in attribute
         model.set_metadata_prop("rtlsim_so", rtlsim_so[0] + "/" + rtlsim_so[1])
         sim_base, sim_rel = rtlsim_so
         # pass in correct tracefile from attribute
         if trace_file == "default":
             trace_file = top_module_file_name + ".wdb"
-        sim = pyxsi_rpcclient.load_sim_obj(sim_base, sim_rel, trace_file)
+        sim = pyxsi_utils.load_sim_obj(sim_base, sim_rel, trace_file)
     else:
         sim_base, sim_rel = rtlsim_so.split("xsim.dir")
         sim_rel = "xsim.dir" + sim_rel
-        sim = pyxsi_rpcclient.load_sim_obj(sim_base, sim_rel, trace_file)
+        sim = pyxsi_utils.load_sim_obj(sim_base, sim_rel, trace_file)
 
     # reset and call rtlsim, including any pre/post hooks
-    pyxsi_rpcclient.reset_rtlsim(sim)
+    pyxsi_utils.reset_rtlsim(sim)
     if pre_hook is not None:
         pre_hook(sim)
-    n_cycles = pyxsi_rpcclient.rtlsim_multi_io(
+    n_cycles = pyxsi_utils.rtlsim_multi_io(
         sim,
         io_dict,
         num_out_values,
@@ -324,7 +320,7 @@ def rtlsim_exec_pyxsi(model, execution_context, pre_hook=None, post_hook=None):
         post_hook(sim)
     # important to call close_rtlsim for pyxsi to flush traces and stop
     # the RPC server process
-    pyxsi_rpcclient.close_rtlsim(sim)
+    pyxsi_utils.close_rtlsim(sim)
 
     # unpack outputs and put back into execution context
     for o, o_vi in enumerate(model.graph.output):

src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py

@@ -29,7 +29,7 @@
 import numpy as np
 import os
 
-import finn.util.pyxsi_rpcclient as pyxsi_rpcclient
+import pyxsi_utils
 from finn.custom_op.fpgadataflow.addstreams import AddStreams
 from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend
 from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
@@ -131,12 +131,12 @@ def execute_node(self, context, graph):
                 super().reset_rtlsim(sim)
                 super().toggle_clk(sim)
             else:
-                pyxsi_rpcclient.reset_rtlsim(sim)
+                pyxsi_utils.reset_rtlsim(sim)
             io_dict = {"inputs": {"in0": rtlsim_inp0, "in1": rtlsim_inp1}, "outputs": {"out": []}}
             self.rtlsim_multi_io(sim, io_dict)
             rtlsim_output = io_dict["outputs"]["out"]
             if rtlsim_backend == "pyxsi":
-                pyxsi_rpcclient.close_rtlsim(sim)
+                pyxsi_utils.close_rtlsim(sim)
             odt = self.get_output_datatype()
             target_bits = odt.bitwidth()
             packed_bits = self.get_outstream_width()

src/finn/custom_op/fpgadataflow/hlsbackend.py

@@ -32,7 +32,7 @@
 from abc import ABC, abstractmethod
 from qonnx.core.datatype import DataType
 
-import finn.util.pyxsi_rpcclient as pyxsi_rpcclient
+import pyxsi_utils
 from finn.custom_op.fpgadataflow import templates
 from finn.util.basic import CppBuilder, get_rtlsim_trace_depth, make_build_dir
 from finn.util.hls import CallHLS
@@ -116,7 +116,7 @@ def prepare_rtlsim(self):
             # save generated lib filename in attribute
             self.set_nodeattr("rtlsim_so", sim.lib._name)
         elif rtlsim_backend == "pyxsi":
-            ret = pyxsi_rpcclient.compile_sim_obj(
+            ret = pyxsi_utils.compile_sim_obj(
                 self.get_verilog_top_module_name(), verilog_files, single_src_dir
             )
             # save generated lib filename in attribute

src/finn/custom_op/fpgadataflow/hwcustomop.py

@@ -41,7 +41,7 @@
 except ModuleNotFoundError:
     PyVerilator = None
 
-import finn.util.pyxsi_rpcclient as pyxsi_rpcclient
+import pyxsi_utils
 
 
 class HWCustomOp(CustomOp):
@@ -141,14 +141,13 @@ def get_rtlsim(self):
             # create PyVerilator wrapper
             sim = PyVerilator(rtlsim_so)
         elif rtlsim_backend == "pyxsi":
-            # load up pyXSI sim using pyxsi_rpcclient
             sim_base, sim_rel = rtlsim_so.split("xsim.dir")
             sim_rel = "xsim.dir" + sim_rel
             # pass in correct tracefile from attribute
             tracefile = self.get_nodeattr("rtlsim_trace")
             if tracefile == "default":
                 tracefile = self.onnx_node.name + ".wdb"
-            sim = pyxsi_rpcclient.load_sim_obj(sim_base, sim_rel, tracefile)
+            sim = pyxsi_utils.load_sim_obj(sim_base, sim_rel, tracefile)
         else:
             assert False, "Unknown rtlsim_backend"
 
@@ -162,7 +161,7 @@ def close_rtlsim(self, sim):
             # no action needed
             pass
         elif rtlsim_backend == "pyxsi":
-            pyxsi_rpcclient.close_rtlsim(sim)
+            pyxsi_utils.close_rtlsim(sim)
         else:
             assert False, "Unknown rtlsim_backend"
 
@@ -231,7 +230,7 @@ def reset_rtlsim(self, sim):
             sim.io.ap_clk = 0
             sim.io.ap_rst_n = 1
         elif rtlsim_backend == "pyxsi":
-            pyxsi_rpcclient.reset_rtlsim(sim)
+            pyxsi_utils.reset_rtlsim(sim)
         else:
             assert False, f"Unknown rtlsim_backend {rtlsim_backend}"
 
@@ -242,7 +241,7 @@ def toggle_clk(self, sim):
             sim.io.ap_clk = 1
             sim.io.ap_clk = 0
         elif rtlsim_backend == "pyxsi":
-            pyxsi_rpcclient.toggle_clk(sim)
+            pyxsi_utils.toggle_clk(sim)
         else:
             assert False, f"Unknown rtlsim_backend {rtlsim_backend}"
 
@@ -265,7 +264,7 @@ def rtlsim_multi_io(self, sim, io_dict):
                 liveness_threshold=pyverilate_get_liveness_threshold_cycles(),
             )
         elif rtlsim_backend == "pyxsi":
-            total_cycle_count = pyxsi_rpcclient.rtlsim_multi_io(
+            total_cycle_count = pyxsi_utils.rtlsim_multi_io(
                 sim, io_dict, num_out_values, sname=sname
             )
         else: