Update llvm-public

clang/include/clang/Basic/BuiltinsAIE.def

@@ -483,8 +483,8 @@ BUILTIN(__builtin_aiev2_get_ctrl_reg, "UiUi", "nc")
 BUILTIN(__builtin_aiev2_get_coreid, "i", "nc")
 
 // Pack-Unpack
-BUILTIN(__builtin_aiev2_pack_I8_I16, "V32cV32sii", "nc")
-BUILTIN(__builtin_aiev2_pack_I4_I8, "V32cV32sii", "nc")
+BUILTIN(__builtin_aiev2_pack_I8_I16, "V32cV32si", "nc")
+BUILTIN(__builtin_aiev2_pack_I4_I8, "V32cV32si", "nc")
 BUILTIN(__builtin_aiev2_unpack_I16_I8, "V32sV32ci", "nc")
 BUILTIN(__builtin_aiev2_unpack_I8_I4, "V32sV32ci", "nc")
 

clang/lib/Headers/aiev2_ldst.h

@@ -12,43 +12,35 @@
 #define __AIEV2_PACK_UNPACK_H__
 
 INTRINSIC(v32int8) pack(v32int16 v, int sign) {
-  return __builtin_aiev2_pack_I8_I16(v, sign,
-                                     __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I8_I16(v, sign);
 }
 
 INTRINSIC(v32uint8) pack(v32uint16 v, int sign) {
-  return __builtin_aiev2_pack_I8_I16(v, sign,
-                                     __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I8_I16(v, sign);
 }
 
 INTRINSIC(v64int4) pack(v64int8 v, int sign) {
-  return __builtin_aiev2_pack_I4_I8(v, sign,
-                                    __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I4_I8(v, sign);
 }
 
 INTRINSIC(v64uint4) pack(v64uint8 v, int sign) {
-  return __builtin_aiev2_pack_I4_I8(v, sign,
-                                    __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I4_I8(v, sign);
 }
 
 INTRINSIC(v32int8) pack(v32int16 v) {
-  return __builtin_aiev2_pack_I8_I16(v, __SIGN_SIGNED,
-                                     __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I8_I16(v, __SIGN_SIGNED);
 }
 
 INTRINSIC(v32uint8) pack(v32uint16 v) {
-  return __builtin_aiev2_pack_I8_I16(v, __SIGN_UNSIGNED,
-                                     __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I8_I16(v, __SIGN_UNSIGNED);
 }
 
 INTRINSIC(v64int4) pack(v64int8 v) {
-  return __builtin_aiev2_pack_I4_I8(v, __SIGN_SIGNED,
-                                    __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I4_I8(v, __SIGN_SIGNED);
 }
 
 INTRINSIC(v64uint4) pack(v64uint8 v) {
-  return __builtin_aiev2_pack_I4_I8(v, __SIGN_UNSIGNED,
-                                    __builtin_aiev2_get_ctrl_reg(crSat));
+  return __builtin_aiev2_pack_I4_I8(v, __SIGN_UNSIGNED);
 }
 
 INTRINSIC(v32int16) unpack(v32int8 v, bool sign) {

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

@@ -4,6 +4,9 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// Modifications (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its
+// affiliates
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the MachineRegisterInfo class.
@@ -976,6 +979,15 @@ class MachineRegisterInfo {
       !isReserved(PhysReg);
   }
 
+  /// Returns true if redundant assignments to \p PhysReg can be simplified.
+  /// This is queried by DeadMachineInstructionElim.
+  /// This essentially means that all assignments of \p PhysReg are visible and
+  /// non volatile.
+  bool canSimplifyPhysReg(MCRegister PhysReg) const {
+    return !isReserved(PhysReg) ||
+           getTargetRegisterInfo()->isSimplifiableReservedReg(PhysReg);
+  }
+
   //===--------------------------------------------------------------------===//
   // LiveIn Management
   //===--------------------------------------------------------------------===//

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -549,6 +549,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return {};
   }
 
+  /// Whether redundant assignments to reserved registers can be simplified by
+  /// e.g. DeadMachineInstructionElim
+  /// See \p MachineRegisterInfo::canSimplifyPhysReg().
+  virtual bool isSimplifiableReservedReg(MCRegister PhysReg) const {
+    return false;
+  }
+
   /// Returns false if we can't guarantee that Physreg, specified as an IR asm
   /// clobber constraint, will be preserved across the statement.
   virtual bool isAsmClobberable(const MachineFunction &MF,

llvm/include/llvm/IR/IntrinsicsAIE2.td

@@ -59,27 +59,27 @@ class AIEV2I1024I1024ADDMACConf
 
 class AIEV2I1024I1024MULConfBF16
       : Intrinsic<[llvm_v8i64_ty], [llvm_v64bf16_ty, llvm_v32bf16_ty, llvm_i128_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2I1024I1024MACConfBF16
       : Intrinsic<[llvm_v8i64_ty], [llvm_v64bf16_ty, llvm_v32bf16_ty, llvm_i128_ty, llvm_v8i64_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2I1024I1024ADDMACConfBF16
       : Intrinsic<[llvm_v8i64_ty], [llvm_v64bf16_ty, llvm_v32bf16_ty, llvm_i128_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2I512I1024MULConfBF16
       : Intrinsic<[llvm_v8i64_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_i128_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2I512I1024MACConfBF16
       : Intrinsic<[llvm_v8i64_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_i128_ty, llvm_v8i64_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2I512I1024ADDMACConfBF16
       : Intrinsic<[llvm_v8i64_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_i128_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2I512I512MULConf
 	 : Intrinsic<[llvm_v16i64_ty], [llvm_v64i8_ty, llvm_v16i32_ty, llvm_i32_ty],
@@ -93,24 +93,29 @@ class AIEV2I512I512AddMaconf
 
 class AIE2bf16MULConf
     : Intrinsic<[llvm_v8i64_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_i32_ty],
-		       [IntrNoMem]>;
-class AIE2bf16MACConf
+	   	       [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIE2bf16MACConf 
     : Intrinsic<[llvm_v8i64_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_v8i64_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
-class AIE2bf16AddMACConf
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIE2bf16AddMACConf 
     : Intrinsic<[llvm_v8i64_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
-
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
+ 
 class AIEV2AddSubAcc : DefaultAttrsIntrinsic<[llvm_v16i64_ty], [llvm_v16i64_ty, llvm_v16i64_ty, llvm_i32_ty],
 					 [IntrNoMem]>;
 
-class AIEV2AddSubAccFloat : DefaultAttrsIntrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty],
-                              [IntrNoMem]>;
+class AIEV2AddSubAccFloat : DefaultAttrsIntrinsic<[llvm_v8i64_ty],
+[llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty],
+[IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2NEGCONF : DefaultAttrsIntrinsic<[llvm_v16i64_ty], [llvm_v16i64_ty, llvm_i32_ty], [IntrNoMem]>;
-class AIEV2NEGFPCONF : DefaultAttrsIntrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_i32_ty], [IntrNoMem]>;
+class AIEV2NEGFPCONF : DefaultAttrsIntrinsic<[llvm_v8i64_ty],
+                                             [llvm_v8i64_ty, llvm_i32_ty],
+                                             [IntrReadMem, IntrInaccessibleMemOnly]>;
 
-class AIEV2V16AccFloatToV16Bf : Intrinsic<[llvm_v16bf16_ty], [llvm_v8i64_ty], [IntrNoMem]>;
+class AIEV2V16AccFloatToV16Bf : Intrinsic<[llvm_v16bf16_ty],
+                                          [llvm_v8i64_ty],
+                                          [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2V16BfToV16AccFloat : Intrinsic<[llvm_v8i64_ty], [llvm_v16bf16_ty], [IntrNoMem]>;
 
 class AIEV2UNDV4Int32
@@ -314,30 +319,42 @@ class AIEV2Concat_1024_512_acc
 //srs
 class AIEV2I256V16Acc32I
 	 : Intrinsic<[llvm_v16i16_ty], [llvm_v8i64_ty, llvm_i32_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2I256V16Acc64I
 	 : Intrinsic<[llvm_v16i16_ty], [llvm_v16i64_ty, llvm_i32_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2I256V32Acc32I
 	 : Intrinsic<[llvm_v32i8_ty], [llvm_v16i64_ty, llvm_i32_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2I256V8Acc64I
 	 : Intrinsic<[llvm_v8i32_ty], [llvm_v8i64_ty, llvm_i32_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2I512V16Acc64I
 	 : Intrinsic<[llvm_v16i32_ty], [llvm_v16i64_ty, llvm_i32_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2I512V32Acc32I
 	 : Intrinsic<[llvm_v32i16_ty], [llvm_v16i64_ty, llvm_i32_ty, llvm_i32_ty],
-					 [IntrNoMem]>;
+					 [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 // VUPS
-class AIEV2Acc32V16I256I : Intrinsic<[llvm_v8i64_ty],  [llvm_v16i16_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-class AIEV2Acc32V32I256I : Intrinsic<[llvm_v16i64_ty], [llvm_v32i8_ty, llvm_i32_ty, llvm_i32_ty],  [IntrNoMem]>;
-class AIEV2Acc32V32I512I : Intrinsic<[llvm_v16i64_ty], [llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-class AIEV2Acc64V16I256I : Intrinsic<[llvm_v16i64_ty], [llvm_v16i16_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-class AIEV2Acc64V16I512I : Intrinsic<[llvm_v16i64_ty], [llvm_v16i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-class AIEV2Acc64V8I256I  : Intrinsic<[llvm_v8i64_ty],  [llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty],  [IntrNoMem]>;
+class AIEV2Acc32V16I256I : Intrinsic<[llvm_v8i64_ty],
+                              [llvm_v16i16_ty, llvm_i32_ty, llvm_i32_ty],
+                              [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIEV2Acc32V32I256I : Intrinsic<[llvm_v16i64_ty],
+                              [llvm_v32i8_ty, llvm_i32_ty, llvm_i32_ty],
+                              [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIEV2Acc32V32I512I : Intrinsic<[llvm_v16i64_ty],
+                              [llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty],
+                              [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIEV2Acc64V16I256I : Intrinsic<[llvm_v16i64_ty],
+                              [llvm_v16i16_ty, llvm_i32_ty, llvm_i32_ty],
+                              [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIEV2Acc64V16I512I : Intrinsic<[llvm_v16i64_ty],
+                              [llvm_v16i32_ty, llvm_i32_ty, llvm_i32_ty],
+                              [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIEV2Acc64V8I256I  : Intrinsic<[llvm_v8i64_ty],
+                              [llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty],
+                              [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 class AIEV2V64I8V2I32V64I8I32 : DefaultAttrsIntrinsic<[llvm_v64i8_ty, llvm_v2i32_ty], [llvm_v64i8_ty, llvm_i32_ty], [IntrNoMem]>;
 class AIEV2V32I16I32V32I16I32 : DefaultAttrsIntrinsic<[llvm_v32i16_ty, llvm_i32_ty], [llvm_v32i16_ty, llvm_i32_ty], [IntrNoMem]>;
@@ -427,7 +444,7 @@ class AIEV2BF16ToInt : Intrinsic<[llvm_i32_ty],
       [IntrNoMem]>;
 class AIEV2V16BF16ToV16I : Intrinsic<[llvm_v16i32_ty],
       [llvm_v16bf16_ty, llvm_i32_ty],
-      [IntrNoMem]>;
+      [IntrReadMem, IntrInaccessibleMemOnly]>;
 
 // Streams
 class AIEV2V16I32I32I32 : DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_i32_ty], [IntrInaccessibleMemOnly]>;
@@ -469,16 +486,16 @@ class AIEV2CLB : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 class AIEV2DIVS : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 
 // Pack-Unpack
-class AIEV2PackI4I8 : Intrinsic<[llvm_v32i8_ty], [llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 
-class AIEV2PackI8I16 : Intrinsic<[llvm_v32i8_ty], [llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;  
+class AIEV2PackI4I8 : Intrinsic<[llvm_v32i8_ty], [llvm_v32i16_ty, llvm_i32_ty], [IntrReadMem, IntrInaccessibleMemOnly]>;
+class AIEV2PackI8I16 : Intrinsic<[llvm_v32i8_ty], [llvm_v32i16_ty, llvm_i32_ty], [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2UnPackI8I4 : Intrinsic<[llvm_v32i16_ty], [llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
 class AIEV2UnPackI16I8 : Intrinsic<[llvm_v32i16_ty], [llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
 
 // Scheduling barrier
 class AIEV2SchedBarrier : Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn]>;
 
 // clear accumulator
-class AIEV2CLR16F : Intrinsic<[llvm_v8i64_ty], [], [IntrNoMem]>;
+class AIEV2CLR16F : Intrinsic<[llvm_v8i64_ty], [], [IntrReadMem, IntrInaccessibleMemOnly]>;
 class AIEV2VCLRACC1024 : Intrinsic<[llvm_v16i64_ty], [], [IntrNoMem]>;
 
 // Extract Sub-Vector

llvm/include/llvm/Target/Target.td

@@ -560,6 +560,11 @@ class Instruction : InstructionEncoding {
   // Added complexity passed onto matching pattern.
   int AddedComplexity  = 0;
 
+  // Passed onto matching pattern and helps in skipping checks
+  // where mayLoad/mayStore is inferred in the instruction but doesn't
+  // mirror in the pattern.
+  bit ModelsInaccessibleMemThroughRegs = false;
+
   // Indicates if this is a pre-isel opcode that should be
   // legalized/regbankselected/selected.
   bit isPreISelOpcode = false;

llvm/include/llvm/Target/TargetSelectionDAG.td

@@ -4,6 +4,8 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// Modifications (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the target-independent interfaces used by SelectionDAG
@@ -1935,9 +1937,11 @@ def atomic_store_64 :
 // their GPRs).
 //
 
-class Pattern<dag patternToMatch, list<dag> resultInstrs> {
+class Pattern<dag patternToMatch, list<dag> resultInstrs,
+              bit modelsInaccessibleMemThroughRegs = false> {
   dag             PatternToMatch  = patternToMatch;
   list<dag>       ResultInstrs    = resultInstrs;
+  bit             ModelsInaccessibleMemThroughRegs = modelsInaccessibleMemThroughRegs;
   list<Predicate> Predicates      = [];  // See class Instruction in Target.td.
   int             AddedComplexity = 0;   // See class Instruction in Target.td.
 }
@@ -1946,6 +1950,7 @@ class Pattern<dag patternToMatch, list<dag> resultInstrs> {
 // not needing a full list.
 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
 
+class PatInaccessibleMem<dag pattern, dag result>: Pattern<pattern, [result], true>;
 //===----------------------------------------------------------------------===//
 // Complex pattern definitions.
 //

llvm/lib/CodeGen/DeadMachineInstructionElim.cpp

@@ -4,6 +4,9 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// Modifications (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its
+// affiliates
+//
 //===----------------------------------------------------------------------===//
 //
 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
@@ -34,11 +37,15 @@ namespace {
     const MachineRegisterInfo *MRI = nullptr;
     const TargetInstrInfo *TII = nullptr;
     LiveRegUnits LivePhysRegs;
+    bool KeepLifetimeInstructions;
 
   public:
     static char ID; // Pass identification, replacement for typeid
-    DeadMachineInstructionElim() : MachineFunctionPass(ID) {
-     initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
+    DeadMachineInstructionElim(bool LifetimeInstructions = false)
+        : MachineFunctionPass(ID),
+          KeepLifetimeInstructions(LifetimeInstructions) {
+      initializeDeadMachineInstructionElimPass(
+          *PassRegistry::getPassRegistry());
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -69,6 +76,15 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
   if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
     return false;
 
+  // Don't delete marks of start and end of lifetime of a stack, as they give
+  // information about lifetime of stack for next passes.
+  if (KeepLifetimeInstructions) {
+    if (MI->getOpcode() == TargetOpcode::LIFETIME_START ||
+        MI->getOpcode() == TargetOpcode::LIFETIME_END) {
+      return false;
+    }
+  }
+
   // Don't delete instructions with side effects.
   bool SawStore = false;
   if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
@@ -78,8 +94,8 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
   for (const MachineOperand &MO : MI->all_defs()) {
     Register Reg = MO.getReg();
     if (Reg.isPhysical()) {
-      // Don't delete live physreg defs, or any reserved register defs.
-      if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
+      // Don't delete live physreg defs, or any non-simplifiable physreg defs.
+      if (!LivePhysRegs.available(Reg) || !MRI->canSimplifyPhysReg(Reg))
         return false;
     } else {
       if (MO.isDead()) {
@@ -127,6 +143,14 @@ bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) {
   for (MachineBasicBlock *MBB : post_order(&MF)) {
     LivePhysRegs.addLiveOuts(*MBB);
 
+    // Reserved registers are considered always live, so consider them as
+    // live-outs for MBB. Inside MBB, dead assignments can still be detected.
+    for (MCPhysReg PhysReg : MRI->getReservedRegs().set_bits()) {
+      if (MRI->canSimplifyPhysReg(PhysReg)) {
+        LivePhysRegs.addReg(PhysReg);
+      }
+    }
+
     // Now scan the instructions and delete dead ones, tracking physreg
     // liveness as we go.
     for (MachineInstr &MI : make_early_inc_range(reverse(*MBB))) {
@@ -149,3 +173,10 @@ bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) {
   LivePhysRegs.clear();
   return AnyChanges;
 }
+
+namespace llvm {
+MachineFunctionPass *
+createDeadMachineInstructionElim(bool KeepLifetimeInstructions = false) {
+  return new DeadMachineInstructionElim(KeepLifetimeInstructions);
+}
+} // end namespace llvm