Milestone Meeting Three

Third Upstream Attempt

The third upstream attempt (for the Netduino 2) can be seen here: https://lists.nongnu.org/archive/html/qemu-devel/2014-09/msg02806.html

This patch received comments and one of them was even reviewed by Peter C. Hopefully the next attempt can gain more traction and be accepted soon. Most of the comments were fairly trivial, just small fixes, no major issues

Fourth Upstream Attempt

The fourth upstream attempt (for the Netduino 2) can be seen here: https://lists.nongnu.org/archive/html/qemu-devel/2014-09/msg03815.html

Includes all changes based on the third upstream attempt. Should be getting close to being accepted.

Some small comments have been made by Peter C. Looks close to having no issues

SPI, NRF24L01Plus, ADC, PWM

These devices (or modes) have all been added to QEMU

SPI

This device adds a SPI bus. This can be used to run CSSE3010 project 1 from 2013 without any changes.

NRF240L01Plus

This device can be connected to the SPI controller. The device uses a simple internal state machine and allows simple register I/O. There is very little other internal functionality at the moment. Not sure how to implement that as it requires an external device for communication. It does allow simple testing at the moment though.

A possibility would be to hard code certain common responses to allow simple testing by students.

ADC

The ADC peripheral generates random values for the ADC. The ADC device does not support injection mode. At the moment it only supports simple value reading.

PWM

The timer device (still only timer 2 to 5) now allows PWM output. The value that is being displayed has had almost no testing though. The calculations aren't super robust so might be inaccurate with different clock scalars. This can be easily fixed by conducting more testing/trial and error.

External Interrupts (EXTI)

The GPIO lines are connected as follows:

1. GPIO devices (There are 9 devices)
   • Each device has 16 outputs
2. SYSCFG device
   • SYSCFG has (16 * 9) inputs
   • This device does the masking based on register values
     • This masking needs to be a bit more robust, but will do for now
3. EXTI device
   • Has 15 GPIO inputs
   • Directly maps these inputs to interrupt outputs

GPIO Controller

Has external access via TCP to a testing Python script using Biffers work. Can read, write and generate interrupts. The Python script is pretty dodgy, but can be used for simple testing. It also slows QEMU down a lot, will probably need to implement a if(changed) check on the QEMU register read/writes