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Refactoring circuit.py Class #4538

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Apr 19, 2024
Merged

Refactoring circuit.py Class #4538

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ca6388e
Refactoring circuit.py Class
Apr 18, 2024
a87189f
fixed ut
Apr 18, 2024
e46c1e7
fixed ut
Apr 18, 2024
f623a2e
fixed method arguments
Apr 19, 2024
8ad24d3
Apply suggestions from code review
maxcapodi78 Apr 19, 2024
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5 changes: 1 addition & 4 deletions _unittest/test_12_PostProcessing.py
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Original file line number Diff line number Diff line change
Expand Up @@ -387,10 +387,7 @@ def test_18_diff_plot(self, diff_test):
assert data1.plot(formula="phaserad", snapshot_path=os.path.join(self.local_scratch.path, "temp9.jpg"))

assert diff_test.create_touchstone_report(
plot_name="Diff_plot",
curvenames=["dB(S(Diff1, Diff1))"],
solution_name="LinearFrequency",
differential_pairs=True,
name="Diff_plot", curves=["dB(S(Diff1, Diff1))"], solution="LinearFrequency", differential_pairs=True
)

@pytest.mark.skipif(is_linux, reason="Failing on Linux")
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26 changes: 13 additions & 13 deletions _unittest/test_21_Circuit.py
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Original file line number Diff line number Diff line change
Expand Up @@ -349,14 +349,14 @@ def test_26_component_catalog(self):

def test_27_set_differential_pairs(self):
assert self.circuitprj.set_differential_pair(
positive_terminal="Port3",
negative_terminal="Port4",
common_name=None,
diff_name=None,
common_ref_z=34,
diff_ref_z=123,
assignment="Port3",
reference="Port4",
common_mode=None,
differential_mode=None,
common_reference=34,
differential_reference=123,
)
assert self.circuitprj.set_differential_pair(positive_terminal="Port3", negative_terminal="Port5")
assert self.circuitprj.set_differential_pair(assignment="Port3", reference="Port5")

def test_28_load_and_save_diff_pair_file(self):
diff_def_file = os.path.join(local_path, "example_models", test_subfolder, "differential_pairs_definition.txt")
Expand Down Expand Up @@ -839,7 +839,7 @@ def test_47_automatic_lna(self):
touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)

status, diff_pairs, comm_pairs = self.aedtapp.create_lna_schematic_from_snp(
touchstone=touchstone_file,
input_file=touchstone_file,
start_frequency=0,
stop_frequency=70,
auto_assign_diff_pairs=True,
Expand All @@ -853,33 +853,33 @@ def test_48_automatic_tdr(self):
touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)

result, tdr_probe_name = self.aedtapp.create_tdr_schematic_from_snp(
touchstone=touchstone_file,
input_file=touchstone_file,
probe_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
probe_ref_pins=["A-MII-RXD1_65.SQFP20X20_144.N"],
termination_pins=["A-MII-RXD2_32.SQFP28X28_208.P", "A-MII-RXD2_66.SQFP20X20_144.N"],
differential=True,
design_name="TDR",
rise_time=35,
use_convolution=True,
analyze=False,
design_name="TDR",
)
assert result

def test_49_automatic_ami(self):
touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
ami_file = os.path.join(local_path, "example_models", test_subfolder, "pcieg5_32gt.ibs")
result, eye_curve_tx, eye_curve_rx = self.aedtapp.create_ami_schematic_from_snp(
touchstone=touchstone_file,
input_file=touchstone_file,
ibis_ami=ami_file,
component_name="Spec_Model",
tx_buffer_name="1p",
rx_buffer_name="2p",
use_ibis_buffer=False,
differential=True,
tx_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
tx_refs=["A-MII-RXD1_65.SQFP20X20_144.N"],
rx_pins=["A-MII-RXD2_32.SQFP28X28_208.P"],
rx_refs=["A-MII-RXD2_66.SQFP20X20_144.N"],
use_ibis_buffer=False,
differential=True,
bit_pattern="random_bit_count=2.5e3 random_seed=1",
unit_interval="31.25ps",
use_convolution=True,
Expand Down
6 changes: 3 additions & 3 deletions _unittest_solvers/test_00_analyze.py
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Original file line number Diff line number Diff line change
Expand Up @@ -392,13 +392,13 @@ def test_05c_circuit_push_excitation(self, circuit_app):
setup_name = "test_07a_LNA"
setup = circuit_app.create_setup(setup_name)
setup.add_sweep_step(start_point=0, end_point=5, step_size=0.01)
assert circuit_app.push_excitations(instance_name="U1", setup_name=setup_name, thevenin_calculation=False)
assert circuit_app.push_excitations(instance_name="U1", setup_name=setup_name, thevenin_calculation=True)
assert circuit_app.push_excitations(instance="U1", thevenin_calculation=False, setup=setup_name)
assert circuit_app.push_excitations(instance="U1", thevenin_calculation=True, setup=setup_name)

def test_05d_circuit_push_excitation_time(self, circuit_app):
setup_name = "test_07b_Transient"
setup = circuit_app.create_setup(setup_name, setup_type="NexximTransient")
assert circuit_app.push_time_excitations(instance_name="U1", setup_name=setup_name)
assert circuit_app.push_time_excitations(instance="U1", setup=setup_name)

def test_06_m3d_harmonic_forces(self, m3dtransient):
assert m3dtransient.enable_harmonic_force(["Stator"], force_type=2, window_function="Rectangular",
Expand Down
2 changes: 1 addition & 1 deletion examples/06-Multiphysics/Hfss_Mechanical.py
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Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@
# correct value of losses.

circuit.analyze()
circuit.push_excitations(instance_name="S1", setup_name=setup_name)
circuit.push_excitations(instance="S1", setup=setup_name)


###############################################################################
Expand Down
6 changes: 2 additions & 4 deletions examples/07-Circuit/Circuit_Siwave_Multizones.py
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Original file line number Diff line number Diff line change
Expand Up @@ -94,10 +94,8 @@
###############################################################################
# Define differential pairs
# ~~~~~~~~~~~~~~~~~~~~~~~~~
circuit.set_differential_pair(diff_name="U0", positive_terminal="U0.via_38.B2B_SIGP",
negative_terminal="U0.via_39.B2B_SIGN")
circuit.set_differential_pair(diff_name="U1", positive_terminal="U1.via_32.B2B_SIGP",
negative_terminal="U1.via_33.B2B_SIGN")
circuit.set_differential_pair(assignment="U0.via_38.B2B_SIGP", reference="U0.via_39.B2B_SIGN", differential_mode="U0")
circuit.set_differential_pair(assignment="U1.via_32.B2B_SIGP", reference="U1.via_33.B2B_SIGN", differential_mode="U1")

###############################################################################
# Plot results
Expand Down
60 changes: 24 additions & 36 deletions examples/07-Circuit/Virtual_Compliance.py
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Original file line number Diff line number Diff line change
Expand Up @@ -72,14 +72,10 @@
# and generate frequency domain reports.

cir = pyaedt.Circuit(projectname=h3d.project_name, designname="Touchstone")
status, diff_pairs, comm_pairs = cir.create_lna_schematic_from_snp(touchstone=touchstone_path,
start_frequency=0,
stop_frequency=70,
auto_assign_diff_pairs=True,
separation=".",
pattern=["component", "pin", "net"],
analyze=True
)
status, diff_pairs, comm_pairs = cir.create_lna_schematic_from_snp(input_file=touchstone_path, start_frequency=0,
stop_frequency=70, auto_assign_diff_pairs=True,
separation=".", pattern=["component", "pin", "net"],
analyze=True)

insertion = cir.get_all_insertion_loss_list(trlist=diff_pairs,
reclist=diff_pairs,
Expand All @@ -104,40 +100,32 @@
# the TDR measurement on a differential pair.
# The original circuit schematic is duplicated and modified to achieve this target.

result, tdr_probe_name = cir.create_tdr_schematic_from_snp(touchstone=touchstone_path,
probe_pins=["X1.A2.PCIe_Gen4_RX0_P"],
probe_ref_pins=["X1.A3.PCIe_Gen4_RX0_N"],
termination_pins=["U1.AP26.PCIe_Gen4_RX0_P",
"U1.AN26.PCIe_Gen4_RX0_N"],
differential=True,
design_name="TDR",
rise_time=35,
use_convolution=True,
analyze=True,
)
result, tdr_probe_name = cir.create_tdr_schematic_from_snp(input_file=touchstone_path,
probe_pins=["X1.A2.PCIe_Gen4_RX0_P"],
probe_ref_pins=["X1.A3.PCIe_Gen4_RX0_N"],
termination_pins=["U1.AP26.PCIe_Gen4_RX0_P",
"U1.AN26.PCIe_Gen4_RX0_N"],
differential=True, rise_time=35, use_convolution=True,
analyze=True, design_name="TDR")

###############################################################################
# Create AMI project
# ~~~~~~~~~~~~~~~~~~
# Create an Ibis AMI project to compute an eye diagram simulation and retrieve
# eye mask violations.
result, eye_curve_tx, eye_curve_rx = cir.create_ami_schematic_from_snp(touchstone=touchstone_path,
ibis_ami=os.path.join(projectdir, "models", "pcieg5_32gt.ibs"),
component_name="Spec_Model",
tx_buffer_name="1p",
rx_buffer_name="2p",
use_ibis_buffer=False,
differential=True,
tx_pins=["U1.AM25.PCIe_Gen4_TX0_CAP_P"],
tx_refs=["U1.AL25.PCIe_Gen4_TX0_CAP_N"],
rx_pins=["X1.B2.PCIe_Gen4_TX0_P"],
rx_refs=["X1.B3.PCIe_Gen4_TX0_N"],
bit_pattern="random_bit_count=2.5e3 random_seed=1",
unit_interval="31.25ps",
use_convolution=True,
analyze=True,
design_name="AMI",
)
result, eye_curve_tx, eye_curve_rx = cir.create_ami_schematic_from_snp(input_file=touchstone_path,
ibis_ami=os.path.join(projectdir, "models",
"pcieg5_32gt.ibs"),
component_name="Spec_Model", tx_buffer_name="1p",
rx_buffer_name="2p",
tx_pins=["U1.AM25.PCIe_Gen4_TX0_CAP_P"],
tx_refs=["U1.AL25.PCIe_Gen4_TX0_CAP_N"],
rx_pins=["X1.B2.PCIe_Gen4_TX0_P"],
rx_refs=["X1.B3.PCIe_Gen4_TX0_N"],
use_ibis_buffer=False, differential=True,
bit_pattern="random_bit_count=2.5e3 random_seed=1",
unit_interval="31.25ps", use_convolution=True,
analyze=True, design_name="AMI")

cir.save_project()

Expand Down
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