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[SYCL][NFC][Doc] Update sycl_ext_intel_device_info backend limitations #16792

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Feb 6, 2025
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[SYCL][NFC][Doc] Update sycl_ext_intel_device_info backend limitations #16792

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[SYCL][NFC][Doc] Update sycl_ext_intel_device_info backend limitations
KseniyaTikhomirova Jan 27, 2025
0620cdb
remove mentions of specific backend
KseniyaTikhomirova Feb 6, 2025
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17 changes: 1 addition & 16 deletions sycl/doc/extensions/supported/sycl_ext_intel_device_info.md
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Expand Up @@ -62,7 +62,7 @@ The device ID can be obtained using the standard get\_info() interface.

A new device descriptor will be added which will provide the device Universal Unique ID (UUID).

This new device descriptor is currently only available for devices in the Level Zero platform, and the matching aspect is only true for those devices. The DPC++ default behavior would be to expose the UUIDs of all supported devices which enables detection of total number of unique devices.
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The DPC++ default behavior would be to expose the UUIDs of all supported devices which enables detection of total number of unique devices.


## Version ##
Expand Down Expand Up @@ -100,11 +100,6 @@ The UUID can be obtained using the standard get\_info() interface.

A new device descriptor will be added which will provide the PCI address in BDF format. BDF format contains the address as: `domain:bus:device.function`.

This new device descriptor is only available for devices in the Level Zero platform, and the matching aspect is only true for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.
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**Note:** The environment variable SYCL\_ENABLE\_PCI must be set to 1 to obtain the PCI address.


## Version ##

All versions of the extension support this query.
Expand Down Expand Up @@ -140,8 +135,6 @@ The PCI address can be obtained using the standard get\_info() interface.

A new device descriptor will be added which will provide the physical SIMD width of an execution unit on an Intel GPU. This data will be used to calculate the computational capabilities of the device.

This new device descriptor is only available for devices in the Level Zero platform, and the matching aspect is only true for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.


## Version ##

Expand Down Expand Up @@ -180,8 +173,6 @@ A new device descriptor will be added which will provide the number of execution

This new device descriptor will provide the same information as "max\_compute\_units" does today. We would like to have an API which is specific for Intel GPUs.

This new device descriptor is only available for devices in the Level Zero platform, and the matching aspect is only true for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.


## Version ##

Expand Down Expand Up @@ -355,8 +346,6 @@ Then the number of hardware threads per EU can be obtained using the standard ge

A new device descriptor will be added which will provide the maximum memory bandwidth. If the device is a subdevice, then the maximum bandwidth of the subdevice is returned.

This new device descriptor is only available for devices in the Level Zero platform, and the matching aspect is only true for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.
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## Version ##

Expand Down Expand Up @@ -397,8 +386,6 @@ Beware that when other processes or threads are using this device when this call
is made, the value it returns may be stale even before it is returned to the
caller.

This new device descriptor is only available for devices in the Level Zero platform, and the matching aspect is only true for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.
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## Version ##

Expand Down Expand Up @@ -435,7 +422,6 @@ Then the free device memory can be obtained using the standard get\_info() inte

A new device descriptor is added which provides the maximum clock rate of device's global memory.

This new device descriptor is not available for devices in the OpenCL platform, and the matching aspect is false for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.
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## Version ##

Expand Down Expand Up @@ -472,7 +458,6 @@ Then the memory clock rate can be obtained using the standard get\_info() interf

A new device descriptor is added which provides the maximum bus width between device and memory.

This new device descriptor is not available for devices in the OpenCL platform, and the matching aspect is false for those devices. The DPC++ default behavior is to expose GPU devices through the Level Zero platform.
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## Version ##

Expand Down