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Save complex OS-level I/O to know the CPU topology #216

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Save complex OS-level I/O to know the CPU topology #216

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Save complex OS-level I/O to know the CPU topology
franz1981 Jan 8, 2025
1d1403f
Address David comments
franz1981 Jan 8, 2025
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17 changes: 3 additions & 14 deletions src/main/java/org/jboss/threads/EnhancedQueueExecutor.java
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,6 @@
import javax.management.ObjectInstance;
import javax.management.ObjectName;

import io.smallrye.common.cpu.CacheInfo;
import org.jboss.threads.management.ManageableThreadPoolExecutorService;
import org.jboss.threads.management.StandardThreadPoolMXBean;

Expand Down Expand Up @@ -123,13 +122,6 @@ public final class EnhancedQueueExecutor extends AbstractExecutorService impleme
// Optimization control flags
// =======================================================

/**
* A global hint which establishes whether it is recommended to disable uses of {@code EnhancedQueueExecutor}.
* This hint defaults to {@code false} but can be changed to {@code true} by setting the {@code jboss.threads.eqe.disable}
* property to {@code true} before this class is initialized.
*/
public static final boolean DISABLE_HINT = readBooleanPropertyPrefixed("disable", false);

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/**
* Update the summary statistics.
*/
Expand Down Expand Up @@ -337,13 +329,10 @@ private static final class RuntimeFields {
private static final long queueSizeOffset;

static {
int cacheLine = CacheInfo.getSmallestDataCacheLineSize();
if (cacheLine == 0) {
// guess
cacheLine = 64;
}
// this is fine for pretty much 32 and 64 bit x86 and ARM processors; see
// https://github.com/ziglang/zig/blob/0.13.0/lib/std/atomic.zig#L424-L434
// cpu spatial prefetcher can drag 2 cache-lines at once into L2
int pad = cacheLine > 128 ? cacheLine : 128;
int pad = 128;
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int longScale = unsafe.arrayIndexScale(long[].class);
int taskNodeScale = unsafe.arrayIndexScale(TaskNode[].class);
// these fields are in units of array scale
Expand Down
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