ViewIntrinsicOp: Limit to ground types specifically.

llvm · Jan 16, 2025 · 487bf82 · 487bf82
1 parent f806d5c
commit 487bf82
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Showing 2 changed files with 5 additions and 1 deletion.
diff --git a/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td b/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
@@ -239,7 +239,7 @@ def ViewIntrinsicOp : FIRRTLOp<"view", []> {
     debugging in a waveform.  This is _not_ a true SystemVerilog Interface, it
     is only lowered to one.
   }];
-  let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<FIRRTLBaseType>:$inputs);
+  let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<GroundType>:$inputs);
   let assemblyFormat = "$name `,` $augmentedType (`,` $inputs^)? attr-dict (`:` type($inputs)^)?";
 }
 

diff --git a/include/circt/Dialect/FIRRTL/FIRRTLTypes.td b/include/circt/Dialect/FIRRTL/FIRRTLTypes.td
@@ -81,6 +81,10 @@ def AggregateType : FIRRTLDialectType<
   CPred<"type_isa<FVectorType, BundleType, FEnumType>($_self)">,
   "a aggregate type", "::circt::firrtl::FIRRTLBaseType">;
 
+def GroundType : FIRRTLDialectType<
+  CPred<"llvm::isa<FIRRTLBaseType>($_self) && cast<FIRRTLBaseType>($_self).isGround()">,
+  "a ground type", "::circt::firrtl::FIRRTLBaseType">;
+
 def PassiveType : FIRRTLDialectType<
   CPred<"type_isa<FIRRTLBaseType>($_self) && cast<FIRRTLBaseType>($_self).isPassive()">,
   "a passive base type (contain no flips)", "::circt::firrtl::FIRRTLBaseType">;