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Pull requests: llvm/circt

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Pull requests list

Revert "Use MLIR python detection environment (#8037)"
#8038 opened Jan 7, 2025 by mikeurbach Loading…
2
[LLHD] Removing llhd-sim tests LLHD
#8036 opened Jan 7, 2025 by teqdruid Loading…
2
[RTG] Add context resource attribute interface RTG Involving the `rtg` dialect
#8034 opened Jan 6, 2025 by maerhart Loading…
2
[MemoryBanking] Support multi-dimension memory banking
#8033 opened Jan 6, 2025 by jiahanxie353 Loading…
6
Convert ICE40 to BLIF
#8031 opened Jan 5, 2025 by darthscsi • Draft
[FIRRTL] Add View Intrinsic
#8026 opened Jan 3, 2025 by seldridge • Draft
[ImportVerilog] add real literal support, refine real type, and add real format support Moore
#8020 opened Dec 29, 2024 by chenbo-again • Draft
6
Add the BLIF dialect.
#8019 opened Dec 29, 2024 by darthscsi Loading…
1
Add the ICE40 dialect.
#8018 opened Dec 27, 2024 by darthscsi Loading…
5
[ImportVerilog] Add foreach statement support. Moore
#8017 opened Dec 26, 2024 by chenbo-again Loading…
7
[ImportVerilog] Support for Procedural assign statements ImportVerilog Moore
#8010 opened Dec 19, 2024 by owlxiao Loading…
2
[ImportVerilog] sva prototype ImportVerilog Moore
#7999 opened Dec 16, 2024 by chenbo-again • Draft
[RTG][Elaboration] Move ConstantLike check after TypeSwitch for better performance RTG Involving the `rtg` dialect
#7998 opened Dec 16, 2024 by maerhart Loading…
1
[RTG][Elaboration] Do not internalize primitive values RTG Involving the `rtg` dialect
#7997 opened Dec 16, 2024 by maerhart Loading…
[HW] Add pass to outline certain ops: hw-outline-ops HW Involving the `hw` dialect
#7991 opened Dec 13, 2024 by teqdruid Loading…
5
[RTG][Elaboration] Add support for 'scf.if' and 'scf.for' RTG Involving the `rtg` dialect
#7986 opened Dec 13, 2024 by maerhart Loading…
4
[RTG] Add InstructionOpInterface RTG Involving the `rtg` dialect
#7979 opened Dec 12, 2024 by maerhart Loading…
1
[RTG][Elaboration] Add support for 'index.add' and 'index.cmp' RTG Involving the `rtg` dialect
#7978 opened Dec 12, 2024 by maerhart Loading…
2
[Do-Not-Merge][FIRRTL][Sim][SV] Rework printf lowering pipeline
#7973 opened Dec 12, 2024 by fzi-hielscher • Draft
[ImportVerilog] Support for sized unpacked arrays in 'inside' expressions ImportVerilog Moore
#7971 opened Dec 11, 2024 by ladisgin Loading…
11
[RTG][Elaboration] Support sequences RTG Involving the `rtg` dialect
#7969 opened Dec 11, 2024 by maerhart Loading…
Fix temporal code motion
#7959 opened Dec 6, 2024 by AndreyVV-100 Loading…
5
[ImportVerilog] Add case inside ImportVerilog Moore
#7928 opened Dec 1, 2024 by ankolesn Loading…
9
[RTG][Elaboration] Add support for arith constants RTG Involving the `rtg` dialect
#7890 opened Nov 25, 2024 by maerhart • Draft
2
[circt-test] fix SymbiYosys integration test
#7886 opened Nov 24, 2024 by unlsycn Loading…
11
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