[FIRRTL][Sim] Add fopen and fclose intrinsics, add fd operand to printf
#7111
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| return setLoweringTo<sv::SystemFunctionOp>( | ||
| op, resultTy, builder.getStringAttr("fopen"), ValueRange{filename, mode}); |
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$fopen is task so you cannot put this into non-procedural region. Please put this to initial block and assign return value to a register.
| auto result = builder.create<sv::SystemFunctionOp>( | ||
| NoneType::get(builder.getContext()), builder.getStringAttr("fclose"), | ||
| ValueRange{fd}); | ||
| return success(); |
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This also needs to be in a procedural region. I noticed currently there is no support for final statement. That seems reasonable addition to SV dialect.
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Generally the implementation looks great but let's wait for how chipsalliance/firrtl-spec#213 goes first 👍
| StringRef formatString; | ||
| if (parseExp(clock, "expected clock expression in printf") || | ||
| parseExp(condition, "expected condition in printf") || | ||
| parseExp(fd, "expected fd expression in printf") || |
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It 's necessary to accept old syntal. Please add a condition for FIRRTL-spec version.
| node fd = intrinsic(circt_fopen<filename = "file.txt", mode = "a"> : SInt<32>) | ||
| printf(clock, cond, fd, "test %d\n", var) | ||
| intrinsic(circt_fclose, fd) |
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This is pretty problematic as this is introducing a procedural ordering requirement that is not reflected in the IR. I can legally move the close before the printf, yet there is an expectation that I do not and that this will lower to a specific order in Verilog.
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Ah, I was assuming fclose intrinsic is lowered in fclose in final statement. Alternatively we could add clock and enable operands either.
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Closed as in favor of #7983. |
This PR enables the SystemVerilog generated by Chisel&CIRCT can be
fwriteto different files by the simulator.FIRRTL Spec changes: chipsalliance/firrtl-spec#213 (some discussion already there)
Closes #7092, CC @seldridge @sequencer @uenoku