Code

OpenPiton Polara FPGA with plic#4

Code

Open

elisabethumblet wants to merge 23 commits intoopenhwgroup:openpiton_polaraopenhwgroup/core-v-polara-apu:openpiton_polarafrom elisabethumblet:polara_fpga_plic_mergeelisabethumblet/core-v-polara-apu:polara_fpga_plic_mergeCopy head branch name to clipboard

+3,250-176

Commits

Commits on Apr 30, 2024

• Adding Ara RTL to FPGA Protosyn flow

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  cb60496

  Copy full SHA for cb60496

• Adding Alveo U280 board to FPGA Protosyn flow

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  b466c83

  Copy full SHA for b466c83

• Include BD in Protosyn flow

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  affa658

  Copy full SHA for affa658

• Update Polara BD for Protosyn

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  5c006aa

  Copy full SHA for 5c006aa

• Add Alveo U280 config options and IPs

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  aa2f730

  Copy full SHA for aa2f730

• Replaced Polara BD creation file

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  6e5090b

  Copy full SHA for 6e5090b

• [FPGA] Update Alveo U280 constraints

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  5c0d3a7

  Copy full SHA for 5c0d3a7

• [FPGA] Bug fixing on U280 flow

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  e6229a6

  Copy full SHA for e6229a6

• [FPGA] Polara timing fix at 50MHz

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  100aa42

  Copy full SHA for 100aa42

• [FPGA] Fix latches in L2 and BRAM wrapper

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  f3e55d7

  Copy full SHA for f3e55d7

• [FPGA] Update constraints

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  cb5dcd7

  Copy full SHA for cb5dcd7

• [FPGA] Update UART IP frequency config

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  40b49ad

  Copy full SHA for 40b49ad

• Remove old U280 Polara top

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  df94cc3

  Copy full SHA for df94cc3

• [FPGA] Remove debug probes

  

  elisabethumblet

  authored and

  elisabethumblet

  committed
  317cc7f

  Copy full SHA for 317cc7f

• Merge PLIC CLINT to FPGA branch

  

  Yoan Fournier

  authored and

  elisabethumblet

  committed
  f3d6d52

  Copy full SHA for f3d6d52

• Fix merge conflicts PLIC CLINT

  

  Yoan Fournier

  authored and

  elisabethumblet

  committed
  62ce9b0

  Copy full SHA for 62ce9b0

• Fixed PLIC bug

  

  Yoan Fournier

  authored and

  elisabethumblet

  committed
  84eefd8

  Copy full SHA for 84eefd8

• [FPGA] PLIC/CLINT Integration

  

  elisabethumblet

  committed
  7f65643

  Copy full SHA for 7f65643

• [FPGA] Fix plic flist and latch

  

  elisabethumblet

  committed
  60eeea8

  Copy full SHA for 60eeea8

• [FPGA] Add register to interrupt signals in chip, better timing

  

  elisabethumblet

  committed
  86e28fe

  Copy full SHA for 86e28fe

• [FPGA] Update ariane wrapper

  

  elisabethumblet

  committed
  c9f9948

  Copy full SHA for c9f9948

Commits on Jul 30, 2024

• [FPGA] Fix FPGA timing loop in FLL

  

  elisabethumblet

  committed
  09a758b

  Copy full SHA for 09a758b

Commits on Aug 14, 2024

• Format cleanup

  

  elisabethumblet

  committed
  59d38eb

  Copy full SHA for 59d38eb