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Add dcsr.cetrig for Sddbltrp #1005

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wants to merge 14 commits into from
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Add dcsr.cetrig for Sddbltrp #1005

wants to merge 14 commits into from

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rtwfroody
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Private email from Ved:

We discussed this PR in the ARC this week and the suggestion is to include all
of the Sddbltrp into this PR. Here is additional inclusion suggested:

dcsr - bit 19, cetrig, WARL
Smdbltrp extension adds the cetrig (critical-error-trigger) field to dcsr.
When cetrig is set to 1, a hart in a critical error state enters Debug Mode
instead of asserting the critical-error signal to the platform. Upon such
entry into Debug Mode, the cause field is set to 7, and the extcause field
is set to 0, indicating a critical error triggered the Debug Mode entry.
This cause has the highest priority among all reasons for entering Debug
Mode. Resuming from Debug Mode following an entry from the critical error
state returns the hart to the critical error state.

Note:
The implication of this specification is that resuming from Debug Mode,
following an entry due to a critical error, will either result in an
immediate re-entry into Debug Mode due to the critical error if cetrig is
set to 1, or it will cause the critical-error signal to be asserted to the
platform.

rtwfroody and others added 14 commits February 27, 2024 13:08
@rtwfroody
Fix contradictory req. for ndmresetpending
74dbb5b 
Conflicts:
	debug_module.tex
@rtwfroody
Clarify textra behavior when XLEN changes.
bf099ee
@rtwfroody
Change version to 1.0.0-rc2
c6954e1
@rtwfroody
Remove Section 4.9: XLEN
ceb8709 
Section 4.1 already says "Effective XLEN is DXLEN." The statement about
communicating XLEN to the user is unnecessary to the spec, and unclear,
so we don't need it.
@rtwfroody
Merge pull request #984 from riscv/xlen
afd8840 
Remove Section 4.9: XLEN
@rtwfroody
Merge pull request #978 from riscv/csr_xlen
dc06142 
Clarify textra behavior when XLEN changes.
@rtwfroody
Make the data of the *context registers 32 bits wide.
9fab0ac 
Clarify bit recommendations on scontext and mcontext.
@rtwfroody
In Sdtrig, XLEN refers to the current mode.
762ae29 
Not just M-Mode and D-Mode.
@rtwfroody
Merge pull request #951 from JanMatCodasip/fix-contradictory-ndmreset…
a7c19ac 
…pending-requirements

Fix contradictory req. for ndmresetpending
@rtwfroody
Merge pull request #981 from riscv/context
c26ba92 
Make the data of the *context registers 32 bits wide.
@pdonahue-ventana @rtwfroody
Load data before trigger priority was ambiguous.
f8dad44
@rtwfroody
Merge pull request #987 from riscv/load_data_before
c9ccdad 
Load data before trigger priority was ambiguous.
@rtwfroody
Merge branch 'main' into rc2
766491c 
To get some misc asciidoc fixes.
@rtwfroody
Add dcsr.cetrig for Sddbltrp
646d02a
pdonahue-ventana
pdonahue-ventana reviewed Apr 16, 2024
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Why bit 19 instead of bit 18?

@rtwfroody
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Closing in favor of #998.

@rtwfroody rtwfroody closed this Apr 19, 2024
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@rtwfroody @pdonahue-ventana