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Add dcsr.cetrig for Sddbltrp#1005

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rtwfroody wants to merge 14 commits intorc2riscv/riscv-debug-spec:rc2from Sddbltrpriscv/riscv-debug-spec:SddbltrpCopy head branch name to clipboard

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Commits on Feb 27, 2024

• Fix contradictory req. for ndmresetpending

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Commits on Mar 4, 2024

• Clarify textra behavior when XLEN changes.

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Commits on Mar 7, 2024

• Change version to 1.0.0-rc2

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Commits on Mar 12, 2024

• Remove Section 4.9: XLEN

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Commits on Mar 13, 2024

• Merge pull request #984 from riscv/xlen

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• Merge pull request #978 from riscv/csr_xlen

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Commits on Mar 18, 2024

• Make the data of the *context registers 32 bits wide.

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• In Sdtrig, XLEN refers to the current mode.

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• Merge pull request #951 from JanMatCodasip/fix-contradictory-ndmresetpending-requirements

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Commits on Mar 19, 2024

• Merge pull request #981 from riscv/context

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Commits on Mar 21, 2024

• Load data before trigger priority was ambiguous.

  

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• Merge pull request #987 from riscv/load_data_before

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• Merge branch 'main' into rc2

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Commits on Apr 15, 2024

• Add dcsr.cetrig for Sddbltrp

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