Code

SYncing with master#912

Code

Merged

wmat merged 53 commits intoasciidocriscv/riscv-debug-spec:asciidocfrom masterriscv/riscv-debug-spec:masterCopy head branch name to clipboardNov 20, 2023

+237-175

Commits

Commits on Sep 14, 2023

• AR: Remove comment about privspec/CSR behavior

  Show description for 3f0a9e1
  timsifive

  committed
  3f0a9e1

  Copy full SHA for 3f0a9e1

• AR: Clarify what debuggers can assume about MRs

  timsifive

  committed
  2ace90c

  Copy full SHA for 2ace90c

• Merge pull request #874 from riscv/ar_unimplemented

  Show description for fdfbbaf
  timsifive

  authored
  fdfbbaf

  Copy full SHA for fdfbbaf

• Merge pull request #875 from riscv/mr_assumption

  Show description for 0b80f88
  timsifive

  authored
  0b80f88

  Copy full SHA for 0b80f88

Commits on Sep 16, 2023

• Address review comments on debug_defines.h

  en-sc

  committed
  2cd44e5

  Copy full SHA for 2cd44e5

Commits on Sep 18, 2023

• AR: Clarify unimplemented Sdtrig.

  Show description for b4a51a3
  timsifive

  committed
  b4a51a3

  Copy full SHA for b4a51a3

Commits on Sep 19, 2023

• Merge pull request #876 from en-sc/en-sc/gen-printers

  Show description for f546ddf
  timsifive

  authored
  f546ddf

  Copy full SHA for f546ddf

• AR: tcontrol.mie applies to all traps, not just breakpoints

  Show description for 51fc095
  timsifive

  committed
  51fc095

  Copy full SHA for 51fc095

Commits on Sep 26, 2023

• AR: Clarify mcontext/hcontext.

  Show description for 0563d2f
  timsifive

  committed
  0563d2f

  Copy full SHA for 0563d2f

• AR: List which extensions were considered.

  Show description for 3ef1852
  timsifive

  committed
  3ef1852

  Copy full SHA for 3ef1852

• dscratch[01] are DXLEN bits wide.

  Show description for 182beaa
  timsifive

  committed
  182beaa

  Copy full SHA for 182beaa

• Fix debugger examples: use transfer with write

  Show description for 276b60a
  timsifive

  committed
  276b60a

  Copy full SHA for 276b60a

Commits on Sep 28, 2023

• Merge pull request #886 from riscv/transfer

  Show description for 9db0475
  timsifive

  authored
  9db0475

  Copy full SHA for 9db0475

• Merge pull request #881 from riscv/extensions

  Show description for 39e9d45
  timsifive

  authored
  39e9d45

  Copy full SHA for 39e9d45

• Merge pull request #885 from riscv/dscratch_width

  Show description for 28e0df9
  timsifive

  authored
  28e0df9

  Copy full SHA for 28e0df9

• AR: Remove Message Registers.

  Show description for 1aab674
  timsifive

  committed
  1aab674

  Copy full SHA for 1aab674

• Merge pull request #879 from riscv/sdtrig_sdext

  Show description for 7b764de
  timsifive

  authored
  7b764de

  Copy full SHA for 7b764de

• Don't build serial.tex.

  Show description for d404fd9
  timsifive

  committed
  d404fd9

  Copy full SHA for d404fd9

• Tighten up make clean

  Show description for 2e78518
  timsifive

  committed
  2e78518

  Copy full SHA for 2e78518

• Merge pull request #882 from riscv/context

  Show description for 4acc8ce
  timsifive

  authored
  4acc8ce

  Copy full SHA for 4acc8ce

• Merge pull request #878 from riscv/remove_mr

  Show description for ce016c6
  timsifive

  authored
  ce016c6

  Copy full SHA for ce016c6

• Merge pull request #880 from riscv/tcontrol

  Show description for f9e5222
  timsifive

  authored
  f9e5222

  Copy full SHA for f9e5222

• Merge pull request #887 from riscv/makefile

  Show description for eb844b0
  timsifive

  authored
  eb844b0

  Copy full SHA for eb844b0

Commits on Oct 2, 2023

• AR: Clarify section/chapter in Sdext.

  Show description for 6a5800c
  timsifive

  committed
  6a5800c

  Copy full SHA for 6a5800c

• Merge pull request #895 from riscv/chapter

  Show description for 6df3674
  timsifive

  authored
  6df3674

  Copy full SHA for 6df3674

Commits on Oct 3, 2023

• AR: Clarify why icount matches on every trap.

  timsifive

  committed
  a83e118

  Copy full SHA for a83e118

• Merge pull request #896 from riscv/icount

  Show description for 3f73353
  timsifive

  authored
  3f73353

  Copy full SHA for 3f73353

Commits on Oct 4, 2023

• AR: Clarify what tmexttrigger.intctl is for (#898)

  Show description for 9590e02
  

  timsifive

  and

  pdonahue-ventana

  authored
  9590e02

  Copy full SHA for 9590e02

• AR: Define mcontrol* triggers and multiple accesses (#883)

  Show description for 9ddcbcb
  timsifive

  authored
  9ddcbcb

  Copy full SHA for 9ddcbcb

• AR: Clarify triggers and multiple state changes

  Show description for 79e33fb
  timsifive

  committed
  79e33fb

  Copy full SHA for 79e33fb

• Revert "AR: Clarify triggers and multiple state changes"

  Show description for 4aad021
  timsifive

  committed
  4aad021

  Copy full SHA for 4aad021

• AR: Clarify triggers and multiple state changes

  Show description for 1b81755
  timsifive

  committed
  1b81755

  Copy full SHA for 1b81755

• Merge pull request #899 from riscv/multistate

  Show description for 9f44898
  timsifive

  authored
  9f44898

  Copy full SHA for 9f44898

Commits on Oct 5, 2023

• AR: Update priority table from latest privspec

  Show description for aaab8fb
  timsifive

  committed
  aaab8fb

  Copy full SHA for aaab8fb

• Add people with git PRs to credits.

  Show description for 9f3fd6f
  timsifive

  committed
  9f3fd6f

  Copy full SHA for 9f3fd6f

Commits on Oct 6, 2023

• Merge pull request #897 from riscv/priority

  Show description for 79e257b
  timsifive

  authored
  79e257b

  Copy full SHA for 79e257b

• Merge pull request #900 from riscv/credits

  Show description for 393715e
  timsifive

  authored
  393715e

  Copy full SHA for 393715e

Commits on Oct 9, 2023

• AR: Clarify itrigger behavior.

  Show description for b699db6
  timsifive

  committed
  b699db6

  Copy full SHA for b699db6

Commits on Oct 10, 2023

• Merge pull request #901 from riscv/itrigger_det

  Show description for 3a20826
  timsifive

  authored
  3a20826

  Copy full SHA for 3a20826

Commits on Oct 12, 2023

• AR: Clarify itrigger and trigger number translation

  Show description for 92835a8
  timsifive

  committed
  92835a8

  Copy full SHA for 92835a8

• Merge pull request #903 from riscv/itrigger_fire

  Show description for f5b2ed3
  timsifive

  authored
  f5b2ed3

  Copy full SHA for f5b2ed3

• Rebuild PDF.

  timsifive

  committed
  51f5a29

  Copy full SHA for 51f5a29

Commits on Oct 18, 2023

• AR: Comment etrigger limited to 32 exceptions if XLEN=32

  Show description for 01d2935
  timsifive

  committed
  01d2935

  Copy full SHA for 01d2935

Commits on Oct 19, 2023

• AR: Comment itrigger limited to 32 ints if XLEN=32

  Show description for cc901cf
  timsifive

  committed
  cc901cf

  Copy full SHA for cc901cf

• Merge pull request #907 from riscv/etrigger_limit

  Show description for 97684db
  timsifive

  authored
  97684db

  Copy full SHA for 97684db

• Merge pull request #906 from riscv/itrigger_limit

  Show description for 95b06b0
  timsifive

  authored
  95b06b0

  Copy full SHA for 95b06b0

Commits on Oct 20, 2023

• The last field of a register was not printed

  Show description for f3ed7a5
  en-sc

  committed
  f3ed7a5

  Copy full SHA for f3ed7a5

Commits on Oct 23, 2023

• Fix macro generation

  Show description for 44b8d86
  kr-sc

  committed
  44b8d86

  Copy full SHA for 44b8d86

• Merge pull request #902 from kr-sc/kr-sc/fix-register-definitions-prefixes

  Show description for f762968
  timsifive

  authored
  f762968

  Copy full SHA for f762968

Commits on Oct 25, 2023

• Merge pull request #908 from en-sc/en-sc/fix-reg-printers

  Show description for c4d9ff1
  timsifive

  authored
  c4d9ff1

  Copy full SHA for c4d9ff1

Commits on Nov 3, 2023

• Make register dump output more concise.

  Show description for bdae19a
  timsifive

  committed
  bdae19a

  Copy full SHA for bdae19a

Commits on Nov 7, 2023

• Merge pull request #909 from riscv/concise_regdump

  Show description for ece9f18
  timsifive

  authored
  ece9f18

  Copy full SHA for ece9f18

Commits on Nov 13, 2023

• Rebuild PDF.

  timsifive

  committed
  633bddc

  Copy full SHA for 633bddc