SYncing with master

Makefile

@@ -12,7 +12,6 @@ REGISTERS_TEX += dm_registers.tex
 REGISTERS_TEX += sample_registers.tex
 REGISTERS_TEX += abstract_commands.tex
 REGISTERS_TEX += sw_registers.tex
-REGISTERS_TEX += serial.tex
 
 REGISTERS_CHISEL += dm_registers.scala
 REGISTERS_CHISEL += abstract_commands.scala
@@ -92,7 +91,7 @@ chisel: $(REGISTERS_CHISEL)
 
 clean:
 	rm -f $(DRAFT).pdf *.aux $(DRAFT).toc $(DRAFT).log $(REGISTERS_TEX) \
-	    $(REGISTERS_TEX:=.inc) *.o *_no128.S *.h \
+	    $(REGISTERS_TEX:=.inc) *.o *_no128.S debug_defines.[ch] \
 	    $(DRAFT).hst $(DRAFT).pyg debug_defines.* *.scala \
 	    $(NOTES).pdf $(NOTES).toc $(NOTES).log $(NOTES).hst $(NOTES).pyg \
 	    *.idx *.ind *.ilg *.lot *.lof *.out

README.md

@@ -20,7 +20,7 @@ There are two other interesting make targets:
 1. `make debug_defines` creates a C header and implementation files containing
    constants for addresses and fields of all the registers and abstract
    commands, as well as function and structures used to decode register values.
-   An implementation of such decoder can be seen in `debug_register_printers.c/h`.
+   An implementation of such decoder can be seen in `debug_reg_printer.c/h`.
 2. `make chisel` creates scala files for DM registers and abstract commands
    with the same information.
 

Sdext.tex

@@ -9,9 +9,12 @@ \chapter{Sdext (ISA Extension)}
 of the rest.
 
 In order to be compatible with this specification an implementation must
-implement everything described in this section that is not explicitly listed as
+implement everything described in this chapter that is not explicitly listed as
 optional.
 
+If Sdext is implemented and Sdtrig is not implemented, then accessing any of the
+Sdtrig CSRs must raise an illegal instruction exception.
+
 \section{Debug Mode} \label{debugmode}
 
 Debug Mode is a special processor mode used only when a hart is halted for
@@ -22,7 +25,7 @@ \section{Debug Mode} \label{debugmode}
 \begin{steps}{When executing code due to an abstract command, the hart stays in
     Debug Mode and the following apply:}
 \item All implemented instructions operate just as they do in M-mode, unless
-    an exception is mentioned in this section.
+    an exception is mentioned in this list.
 \item All operations are executed with machine mode privilege, except that
     additional Debug Mode CSRs are accessible and
     \FcsrMstatusMprv in \Rmstatus may be ignored according to \FcsrDcsrMprven.
@@ -138,7 +141,7 @@ \subsection{Step Bit In Dcsr} \label{stepBit}
 instead the instruction is treated as a {\tt nop}. This includes {\tt wfi},
 {\tt wrs.sto}, and {\tt wrs.nto}.
 
-\subsection{Icount Trigger}
+\subsection{Icount Trigger} \label{stepIcount}
 
 Native debuggers won't have access to \RcsrDcsr, but can use the \RcsrIcount
 trigger by setting \FcsrIcountCount to 1.

Sdtrig.tex

@@ -114,36 +114,36 @@ \section{Priority}
 
 \begin{table}[H]
 \centering
-\begin{tabular}{|l|r|l|l|}
+\begin{tabulary}{\textwidth}{|l|p{.7in}|p{2.3in}|p{2.5in}|}
   \hline
-  Priority      & Exception & Description & Trigger \\
-                &      Code &             & \\
+  Priority      & Exception Code & Description & Trigger \\
   \hline
   {\em Highest} &          3 & & etrigger \\
                 &          3 & & icount \\
                 &          3 & & itrigger \\
-                &          3 & & mcontrol/mcontrol6 after \\
-                &            & & \hspace{2em}(on previous instruction) \\
+                &          3 & & mcontrol/mcontrol6 after (on previous instruction) \\
                 \hline
                 &          3 & Instruction address breakpoint & mcontrol/mcontrol6 execute address before \\ \hline
-                &         12 & Instruction page fault & \\ \hline
-                &          1 & Instruction access fault & \\ \hline
+                &  12, 20, 1 & During instruction address translation:
+                                First encountered page fault, guest-page fault, or access fault & \\ \hline
+                &          1 & With physical address for instruction:
+                                Instruction access fault & \\ \hline
                 &          3 & & mcontrol/mcontrol6 execute data before \\ \hline
                 &          2 & Illegal instruction & \\
+                &         22 & Virtual instruction & \\
                 &          0 & Instruction address misaligned & \\
-                &   8, 9, 11 & Environment call & \\
+                & 8, 9, 10, 11 & Environment call & \\
                 &          3 & Environment break & \\
-                &          3 & Load/Store/AMO address breakpoint & mcontrol/mcontrol6 load/store address before \\
-                &          3 & & mcontrol/mcontrol6 store data before \\ \hline
-                &          6 & Store/AMO address misaligned & \\
-                &          4 & Load address misaligned & \\ \hline
-                &         15 & Store/AMO page fault & \\
-                &         13 & Load page fault & \\ \hline
-                &          7 & Store/AMO access fault & \\
-                &          5 & Load access fault & \\
-  {\em Lowest}  &          3 & & mcontrol/mcontrol6 load data before \\
-  \hline
-\end{tabular}
+                &          3 & Load/Store/AMO address breakpoint & mcontrol/mcontrol6 load/store address/data before \\ \hline
+                &       4, 6 & Optionally: Load/Store/AMO address misaligned & \\ \hline
+                & 13, 15, 21, 23, 5, 7 & During address translation for an explicit memory access:
+                                    First encountered page fault, guest-page fault, or access fault & \\ \hline
+                & 5, 7       & With physical address for an explicit memory access:
+                                Load/store/AMO access fault & \\ \hline
+                & 4, 6       & If not higher priority:
+                                Load/store/AMO address misaligned & \\ \hline
+  {\em Lowest}  &          3 & & mcontrol/mcontrol6 load data before \\ \hline
+\end{tabulary}
 \caption{Synchronous exception priority in decreasing priority order.}
 \label{tab:priority}
 \end{table}
@@ -319,6 +319,24 @@ \subsection{Cache Operations}
     \end{steps}
 \end{commentary}
 
+\section{Multiple State Change Instructions} \label{sec:multistate}
+
+An instruction that performs multiple architectural state changes (e.g.,
+register updates and/or memory accesses) might cause a trigger to fire at an
+intermediate point in its execution. As a result, architectural state changes up
+to that point might have been performed, while subsequent state changes,
+starting from the event that activated the trigger, might not have been. The
+definition of such an instruction will specify the order in which architectural
+state changes take place. Alternatively, it may state that partial execution is
+not allowed, implying that a mid-execution trigger must prevent any
+architectural state changes from occurring.
+
+Debuggers won't be aware if an instruction has been partially executed. When
+they resume execution, they will execute the same instruction once more.
+Therefore, it's crucial that partially executing the instruction and then
+executing it again leaves the hart in a state closely resembling the state it
+would have been in if the instruction had only been executed once.
+
 \section{Trigger Registers}
 
 These registers are CSRs, accessible using the RISC-V {\tt csr} opcodes and
@@ -358,12 +376,4 @@ \section{Trigger Registers}
 Attempts to access an unimplemented Trigger Register raise an illegal instruction
 exception.
 
-\begin{commentary}
-    Privileged spec v1.12 requires accesses to unimplemented CSRs to raise
-    illegal instruction exceptions, but that may change in the future. Even if
-    it does change, the behavior here overrides it for Sdtrig CSRs for backwards
-    compatibility. This is even true if Sdtrig is not implemented at all, so the
-    discovery algorithm in Section~\ref{sec:trigger} still works.
-\end{commentary}
-
 \input{hwbp_registers.tex}

debug_module.tex

@@ -311,39 +311,6 @@ \section{Halt Groups, Resume Groups, and External Triggers} \label{hrgroups}
 explicitly allowed. In that case it must be possible to discover the groups by
 using \RdmDmcsTwo even if it's not possible to change the configuration.
 
-\section{Message Registers}
-\label{sec:mr}
-
-Message Registers (MRs) are registers that implement fewer features than a
-traditional register. They support just enough features to pass messages back
-and forth.
-
-Only registers whose description explicitly says they may be MRs may be
-implemented as MRs instead of traditional registers. \RdmDataZero through
-\RdmDataEleven may be MRs, used to let the debugger pass arguments to abstract
-commands, and let the DM pass results from abstract commands back.
-
-A traditional dual-ported register contains a single value, which can be
-read/written through both ports. A MR has two ports: PortA and PortB. It
-contains two values: ValueA and ValueB. Only one of these values has defined
-contents at any one time.
-
-\begin{steps}{For an MR:}
-    \item A write to PortA updates ValueA with the written value, and makes
-        ValueB \unspecified.
-    \item A write to PortB updates ValueB with the written value, and makes
-        ValueA \unspecified.
-    \item A read from PortA returns ValueB.
-    \item A read from PortB returns ValueA.
-\end{steps}
-
-\begin{commentary}
-    A regular register can be used to implement an MR. In some FPGAs it is
-    cheaper to trade off storage for muxes, and in that case the storage can be
-    duplicated (one set of bits for sending and one for receiving) to avoid
-    having to implement muxes to read/write data from/to the correct side.
-\end{commentary}
-
 \section{Abstract Commands} \label{abstractcommands}
 
 The DM supports a set of abstract commands, most of which
@@ -373,12 +340,12 @@ \section{Abstract Commands} \label{abstractcommands}
 unavailable, or because they encounter an error during execution.
 
 If the command takes arguments, the debugger
-must write them to the {\tt data} MRs before writing to \RdmCommand. If a
+must write them to the {\tt data} registers before writing to \RdmCommand. If a
 command returns results, the Debug Module must ensure they are placed
-in the {\tt data} MRs before \FdmAbstractcsBusy is cleared.
-Which {\tt data} MRs are used for the arguments is
+in the {\tt data} registers before \FdmAbstractcsBusy is cleared.
+Which {\tt data} registers are used for the arguments is
 described in Table~\ref{tab:datareg}.  In all cases the least-significant word
-is placed in the lowest-numbered {\tt data} MR. The argument width
+is placed in the lowest-numbered {\tt data} register. The argument width
 depends on the command being executed, and is DXLEN where not explicitly
 specified.
 

debug_register_printers.c → debug_reg_printer.c

@@ -5,7 +5,7 @@
 #include <assert.h>
 #include <stdarg.h>
 
-#include "debug_register_printers.h"
+#include "debug_reg_printer.h"
 
 static unsigned int get_len_or_sprintf(char *buf, unsigned int curr, const char *format, ...)
 {
@@ -23,7 +23,7 @@ static unsigned int get_len_or_sprintf(char *buf, unsigned int curr, const char
 	return (unsigned int)length;
 }
 
-static unsigned int print_value(char *buf, unsigned int offset, uint64_t value)
+static unsigned int print_number(char *buf, unsigned int offset, uint64_t value)
 {
 	const char * const format = value > 9 ? "0x%" PRIx64 : "%" PRIx64;
 
@@ -38,7 +38,7 @@ static unsigned int riscv_debug_reg_field_value_to_s(char *buf, unsigned int off
 		NULL;
 
 	if (!field_value_name)
-		return print_value(buf, offset, field_value);
+		return print_number(buf, offset, field_value);
 	return get_len_or_sprintf(buf, offset, "%s", field_value_name);
 }
 
@@ -61,32 +61,47 @@ static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field,
 }
 
 static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset,
-		riscv_debug_reg_field_list_t list, riscv_debug_reg_ctx_t context, uint64_t value)
+	struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex),
+	riscv_debug_reg_ctx_t context, uint64_t value,
+	enum riscv_debug_reg_show show)
 {
 	unsigned int curr = offset;
-	curr += get_len_or_sprintf(buf, curr, " { ");
-	for (; list.get_next; list = list.get_next(context)) {
-		curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
-				riscv_debug_reg_field_value(list.field, value));
-		curr += get_len_or_sprintf(buf, curr, ", ");
+	curr += get_len_or_sprintf(buf, curr, " {");
+	char *separator = "";
+	for (struct riscv_debug_reg_field_list_t list; get_next; get_next = list.get_next) {
+		list = get_next(context);
+
+		uint64_t field_value = riscv_debug_reg_field_value(list.field, value);
+
+		if ((show == RISCV_DEBUG_REG_SHOW_ALL) ||
+				(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 &&
+					(field_value != 0 ||
+						(list.field.values && list.field.values[0]))) ||
+				(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) {
+			curr += get_len_or_sprintf(buf, curr, separator);
+			curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
+							field_value);
+			separator = " ";
+		}
 	}
 	curr += get_len_or_sprintf(buf, curr, "}");
 	return curr - offset;
 }
 
 unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
-		riscv_debug_reg_ctx_t context, uint64_t value)
+		riscv_debug_reg_ctx_t context, uint64_t value,
+		enum riscv_debug_reg_show show)
 {
 	unsigned int length = 0;
 
 	riscv_debug_reg_info_t reg = get_riscv_debug_reg_info(reg_ordinal);
 
 	length += get_len_or_sprintf(buf, length, "%s=", reg.name);
-	length += print_value(buf, length, value);
+	length += print_number(buf, length, value);
 
 	if (reg.get_fields_head)
-		length += riscv_debug_reg_fields_to_s(buf, length, reg.get_fields_head(context),
-				context, value);
+		length += riscv_debug_reg_fields_to_s(buf, length,
+				reg.get_fields_head, context, value, show);
 
 	if (buf)
 		buf[length] = '\0';

debug_register_printers.h → debug_reg_printer.h

@@ -2,6 +2,12 @@
 
 #include "debug_defines.h"
 
+enum riscv_debug_reg_show {
+	RISCV_DEBUG_REG_SHOW_ALL,
+	RISCV_DEBUG_REG_HIDE_ALL_0,
+	RISCV_DEBUG_REG_HIDE_UNNAMED_0,
+};
+
 /**
  * This function is used to fill a buffer with a decoded string representation
  * of register's value.
@@ -25,4 +31,5 @@
  * riscv_debug_reg_to_s(buf, DTM_DMI_ORDINAL, context, <dmi value>);
  */
 unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
-		riscv_debug_reg_ctx_t context, uint64_t value);
+		riscv_debug_reg_ctx_t context, uint64_t value,
+		enum riscv_debug_reg_show show);

debugger_implementation.tex

@@ -210,7 +210,7 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf}
     \hline
     Write & \RdmDataZero & address & \\
     \hline
-    Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\
+    Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\
     \hline
     Write & \RdmCommand & \FacAccessregisterRegno = 0x1008 & Read \Szero \\
     \hline
@@ -233,7 +233,7 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf}
     \hline
     Write & \RdmDataZero & address & \\
     \hline
-    Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\
+    Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\
     \hline
     Write & \RdmCommand & \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Read \Sone, then execute program buffer \\
     \hline
@@ -355,11 +355,11 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf}
     \hline
     Write & \RdmDataZero & address & \\
     \hline
-    Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\
+    Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\
     \hline
     Write & \RdmDataZero & value & \\
     \hline
-    Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\
+    Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\
     \hline
 \end{tabular}
 \medskip
@@ -378,11 +378,11 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf}
     \hline
     Write & \RdmDataZero & address & \\
     \hline
-    Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\
+    Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\
     \hline
     Write & \RdmDataZero & value0 & \\
     \hline
-    Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\
+    Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\
     \hline
     Write & \RdmAbstractauto & \FdmAbstractautoAutoexecdata[0] & Set \FdmAbstractautoAutoexecdata[0] \\
     \hline