Mediatek: mt8196: add platform/core_config/build_config

scripts/docker_build/sof_builder/Dockerfile

@@ -117,6 +117,7 @@ ENV PATH="/home/sof/work/xtensa-imx8ulp-elf/bin:${PATH}"
 ENV PATH="/home/sof/work/xtensa-mt8186-elf/bin:${PATH}"
 ENV PATH="/home/sof/work/xtensa-mt8195-elf/bin:${PATH}"
 ENV PATH="/home/sof/work/xtensa-mt8188-elf/bin:${PATH}"
+ENV PATH="/home/sof/work/xtensa-mt8196-elf/bin:${PATH}"
 
 ARG NEWLIB_REPO=https://github.com/jcmvbkbc/newlib-xtensa.git
 RUN cd "$HOME" && \

scripts/set_xtensa_params.sh

@@ -135,7 +135,11 @@ case "$platform" in
 	HOST="xtensa-mt8195-elf"
 	TOOLCHAIN_VER="RI-2019.1-linux"
 	;;
-
+    mt8196)
+	XTENSA_CORE="HiFi5_MPU_lock_2023_11"
+	HOST="xtensa-mt8196-elf"
+	TOOLCHAIN_VER="RI-2023.11-linux"
+	;;
     *)
 	>&2 printf 'Unknown xtensa platform=%s\n' "$platform"
 	return 1
@@ -144,7 +148,7 @@ esac
 
 # Pre-zephyr "XTOS" build, testbench,...
 case "$platform" in
-    mtl|lnl|ptl|acp_7_0)
+    mtl|lnl|ptl|acp_7_0|mt8196)
 	SOF_CC_BASE='clang';;
     *)
 	SOF_CC_BASE='xcc';;

scripts/xtensa-build-all.sh

@@ -18,7 +18,7 @@ DEFAULT_PLATFORMS=(
 SUPPORTED_PLATFORMS=( "${DEFAULT_PLATFORMS[@]}" )
 
 # Container work is in progress
-SUPPORTED_PLATFORMS+=( acp_6_3 acp_7_0 )
+SUPPORTED_PLATFORMS+=( acp_6_3 acp_7_0 mt8196)
 
 BUILD_ROM=no
 BUILD_DEBUG=no

src/arch/xtensa/CMakeLists.txt

@@ -26,6 +26,8 @@ elseif(CONFIG_MT8188)
         set(platform_folder mt8188)
 elseif(CONFIG_MT8195)
 	set(platform_folder mt8195)
+elseif(CONFIG_MT8196)
+	set(platform_folder mt8196)
 else()
 	message(FATAL_ERROR "Platform not defined, check your Kconfiguration?")
 endif()
@@ -477,7 +479,7 @@ set(UNSIGNED_RI imx8 imx8x imx8m imx8ulp)
 # AMD
 list(APPEND UNSIGNED_RI rn rmb vangogh acp_6_3 acp_7_0)
 # MediaTek
-list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195)
+list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195 mt8196)
 
 if(${fw_name} IN_LIST UNSIGNED_RI) # mere copy
 	add_custom_command(OUTPUT reproducible.ri

src/arch/xtensa/configs/mt8196_defconfig

@@ -0,0 +1,15 @@
+CONFIG_MT8196=y
+CONFIG_CORE_COUNT=1
+CONFIG_COMP_VOLUME=y
+CONFIG_COMP_SRC=n
+CONFIG_COMP_FIR=n
+CONFIG_COMP_IIR=n
+CONFIG_COMP_DCBLOCK=n
+CONFIG_COMP_TDFB=n
+CONFIG_COMP_TONE=n
+CONFIG_COMP_MIXER=n
+CONFIG_COMP_MUX=n
+CONFIG_COMP_KPB=n
+CONFIG_COMP_SEL=n
+CONFIG_COMP_ASRC=n
+CONFIG_DEBUG=y

src/drivers/mediatek/CMakeLists.txt

@@ -7,3 +7,6 @@ endif()
 if(CONFIG_MT8186 OR CONFIG_MT8188)
         add_subdirectory(mt818x)
 endif()
+if(CONFIG_MT8196)
+	add_subdirectory(mt8196)
+endif()

src/drivers/mediatek/mt8196/CMakeLists.txt

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+add_local_sources(sof interrupt.c intc.c intc_map.c ipc.c timer.c)
+

src/drivers/mediatek/mt8196/intc.c

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright(c) 2024 MediaTek. All rights reserved.
+ *
+ * Author: Hailong Fan <[email protected]>
+ */
+
+#include <rtos/interrupt.h>
+#include <sof/lib/memory.h>
+#include <sof/platform.h>
+#include <sof/lib/uuid.h>
+#include <platform/drivers/interrupt.h>
+#include <platform/drivers/intc.h>
+#include <errno.h>
+#include <stdint.h>
+
+SOF_DEFINE_REG_UUID(intc_mt8196);
+DECLARE_TR_CTX(intc_tr, SOF_UUID(intc_mt8196_uuid), LOG_LEVEL_INFO);
+
+static struct intc_desc_t intc_desc;
+
+void intc_init(void)
+{
+	uint32_t word, group, irq;
+
+	for (group = 0; group < INTC_GRP_NUM; group++) {
+		for (word = 0; word < INTC_GRP_LEN; word++)
+			intc_desc.grp_irqs[group][word] = 0x0;
+	}
+
+	for (word = 0; word < INTC_GRP_LEN; word++)
+		intc_desc.int_en[word] = 0x0;
+
+	for (irq = 0; irq < IRQ_MAX_CHANNEL; irq++) {
+		intc_desc.irqs[irq].id = irq;
+		intc_desc.irqs[irq].group = irq2grp_map[irq];
+		intc_desc.irqs[irq].pol = INTC_POL_LOW;
+	}
+
+	for (word = 0; word < INTC_GRP_LEN; word++) {
+		io_reg_write(INTC_IRQ_EN(word), 0x0);
+		io_reg_write(INTC_IRQ_WAKE_EN(word), 0x0);
+		io_reg_write(INTC_IRQ_STAGE1_EN(word), 0x0);
+		io_reg_write(INTC_IRQ_POL(word), 0xFFFFFFFF);
+	}
+
+	for (group = 0; group < INTC_GRP_NUM; group++) {
+		for (word = 0; word < INTC_GRP_LEN; word++)
+			io_reg_write(INTC_IRQ_GRP(group, word), 0x0);
+	}
+}
+
+void intc_irq_unmask(enum IRQn_Type irq)
+{
+	uint32_t word, group;
+
+	if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) {
+		word = INTC_WORD(irq);
+		group = intc_desc.irqs[irq].group;
+		io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), INTC_BIT(irq));
+	} else {
+		tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
+	}
+}
+
+void intc_irq_mask(enum IRQn_Type irq)
+{
+	uint32_t word;
+
+	if (irq < IRQ_MAX_CHANNEL) {
+		word = INTC_WORD(irq);
+		io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), 0);
+	} else {
+		tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
+	}
+}
+
+int intc_irq_enable(enum IRQn_Type irq)
+{
+	uint32_t word, irq_b, group, pol;
+	int ret;
+
+	if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM &&
+	    intc_desc.irqs[irq].pol < INTC_POL_NUM) {
+		word = INTC_WORD(irq);
+		irq_b = INTC_BIT(irq);
+		group = intc_desc.irqs[irq].group;
+		pol = intc_desc.irqs[irq].pol;
+
+		intc_desc.int_en[word] |= irq_b;
+		intc_desc.grp_irqs[group][word] |= irq_b;
+		io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0);
+		if (pol == INTC_POL_HIGH)
+			io_reg_update_bits(INTC_IRQ_POL(word), irq_b, 0);
+		else
+			io_reg_update_bits(INTC_IRQ_POL(word), irq_b, irq_b);
+
+		io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, irq_b);
+		io_reg_update_bits(INTC_IRQ_EN(word), irq_b, irq_b);
+
+		ret = 1;
+	} else {
+		tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
+		ret = 0;
+	}
+
+	return ret;
+}
+
+int intc_irq_disable(enum IRQn_Type irq)
+{
+	uint32_t word, irq_b, group;
+	int ret;
+
+	if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) {
+		word = INTC_WORD(irq);
+		irq_b = INTC_BIT(irq);
+		group = intc_desc.irqs[irq].group;
+
+		intc_desc.int_en[word] &= ~irq_b;
+		intc_desc.grp_irqs[group][word] &= ~irq_b;
+		io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0);
+		io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, 0);
+
+		ret = 1;
+	} else {
+		tr_err(&intc_tr, "INTC fail to disable irq %u\n", irq);
+		ret = 0;
+	}
+
+	return ret;
+}
+

src/drivers/mediatek/mt8196/intc_map.c

@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright(c) 2024 MediaTek. All rights reserved.
+ *
+ * Author: Hailong Fan <[email protected]>
+ */
+
+#include <sof/audio/component_ext.h>
+#include <rtos/interrupt.h>
+#include <sof/lib/memory.h>
+#include <sof/platform.h>
+#include <platform/drivers/timer.h>
+#include <platform/drivers/interrupt.h>
+#include <ipc/stream.h>
+#include <errno.h>
+#include <stdint.h>
+
+const unsigned char grp_pri[INTC_GRP_NUM] = {
+	INTC_GRP0_LEVEL, INTC_GRP1_LEVEL, INTC_GRP2_LEVEL, INTC_GRP3_LEVEL,
+	INTC_GRP4_LEVEL, INTC_GRP5_LEVEL, INTC_GRP6_LEVEL, INTC_GRP7_LEVEL,
+	INTC_GRP8_LEVEL, INTC_GRP9_LEVEL, INTC_GRP10_LEVEL, INTC_GRP11_LEVEL,
+	INTC_GRP12_LEVEL, INTC_GRP13_LEVEL, INTC_GRP14_LEVEL, INTC_GRP15_LEVEL,
+};
+
+const uint8_t irq2grp_map[IRQ_MAX_CHANNEL] = {
+	[CCU_IRQn]           = INTC_GRP1,
+	[SCP_IRQn]           = INTC_GRP1,
+	[SPM_IRQn]           = INTC_GRP1,
+	[PCIE_IRQn]          = INTC_GRP1,
+	[INFRA_HANG_IRQn]    = INTC_GRP1,
+	[PERI_TIMEOUT_IRQn]  = INTC_GRP1,
+	[MBOX_C0_IRQn]       = INTC_GRP2,
+	[MBOX_C1_IRQn]       = INTC_GRP2,
+	[TIMER0_IRQn]        = INTC_GRP1,
+	[TIMER1_IRQn]        = INTC_GRP1,
+	[IPC_C0_IRQn]        = INTC_GRP1,
+	[IPC_C1_IRQn]        = INTC_GRP1,
+	[IPC1_RSV_IRQn]      = INTC_GRP1,
+	[C2C_SW_C0_IRQn]     = INTC_GRP1,
+	[C2C_SW_C1_IRQn]     = INTC_GRP1,
+	[UART_IRQn]          = INTC_GRP12,
+	[UART_BT_IRQn]       = INTC_GRP12,
+	[LATENCY_MON_IRQn]   = INTC_GRP11,
+	[BUS_TRACKER_IRQn]   = INTC_GRP13,
+	[USB0_IRQn]          = INTC_GRP8,
+	[USB1_IRQn]          = INTC_GRP8,
+	[SCPVOW_IRQn]        = NO_GRP,
+	[CCIF3_C0_IRQn]      = INTC_GRP8,
+	[CCIF3_C1_IRQn]      = INTC_GRP8,
+	[PWR_CTRL_IRQn]      = NO_GRP,
+	[DMA_C0_IRQn]        = INTC_GRP10,
+	[DMA_C1_IRQn]        = NO_GRP,
+	[AXI_DMA0_IRQn]      = INTC_GRP9,
+	[AXI_DMA1_IRQn]      = NO_GRP,
+	[AUDIO_C0_IRQn]      = INTC_GRP10,
+	[AUDIO_C1_IRQn]      = INTC_GRP10,
+	[HIFI5_WDT_C0_IRQn]  = INTC_GRP13,
+	[HIFI5_WDT_C1_IRQn]  = INTC_GRP13,
+	[APU_MBOX_C0_IRQn]   = INTC_GRP0,
+	[APU_MBOX_C1_IRQn]   = INTC_GRP0,
+	[TIMER2_IRQn]        = INTC_GRP13,
+	[PWR_ON_C0_IRQ]      = INTC_GRP13,
+	[PWR_ON_C1_IRQ]      = INTC_GRP13,
+	[WAKEUP_SRC_C0_IRQn] = INTC_GRP13,
+	[WAKEUP_SRC_C1_IRQn] = INTC_GRP13,
+	[WDT_IRQn]           = NO_GRP,
+	[CONNSYS1_IRQn]      = INTC_GRP3,
+	[CONNSYS3_IRQn]      = INTC_GRP3,
+	[CONNSYS4_IRQn]      = INTC_GRP3,
+	[CONNSYS2_IRQn]      = INTC_GRP3,
+	[IPIC_IRQn]          = INTC_GRP1,
+	[AXI_DMA2_IRQn]      = INTC_GRP9,
+	[AXI_DMA3_IRQn]      = NO_GRP,
+	[APSRC_DDREN_IRQn]   = INTC_GRP4,
+	[LAT_MON_EMI_IRQn]   = INTC_GRP11,
+	[LAT_MON_INFRA_IRQn] = INTC_GRP11,
+	[DEVAPC_VIO_IRQn]    = INTC_GRP11,
+	[AO_INFRA_HANG_IRQn] = NO_GRP,
+	[BUS_TRA_EMI_IRQn]   = INTC_GRP13,
+	[BUS_TRA_INFRA_IRQn] = INTC_GRP13,
+	[L2SRAM_VIO_IRQn]    = INTC_GRP11,
+	[L2SRAM_SETERR_IRQn] = INTC_GRP11,
+	[PCIERC_GRP2_IRQn]   = INTC_GRP8,
+	[PCIERC_GRP3_IRQn]   = INTC_GRP8,
+};
+
+const uint8_t grp2hifi_irq_map[INTC_GRP_NUM] = {
+	[INTC_GRP0]  = 0,
+	[INTC_GRP1]  = 1,
+	[INTC_GRP2]  = 2,
+	[INTC_GRP3]  = 3,
+	[INTC_GRP4]  = 4,
+	[INTC_GRP5]  = 5,
+	[INTC_GRP6]  = 7,
+	[INTC_GRP7]  = 8,
+	[INTC_GRP8]  = 9,
+	[INTC_GRP9]  = 10,
+	[INTC_GRP10] = 11,
+	[INTC_GRP11] = 16,
+	[INTC_GRP12] = 17,
+	[INTC_GRP13] = 18,
+	[INTC_GRP14] = 20,
+	[INTC_GRP15] = 21,
+};