2024-07

Brno Univ. of Technology, Jul 2024

• Repository renamed to vhdl-course
• Repository folder structure modified
• Challenges sections added to the labs
• Top level schematics redrawn
• List of labs modified
• Arithmetic circuit lab added
• FSM debouncer lab created
• Used Vivado VHDL templates
• generate mechanism added
• RTL and Gate level screenshots added
• Instructions for TerosHDL ver.5 created
• Comments and lab instructions updated
• Solutions updated and TerosHDL comments applied

2023-07

BUT: Digital electronics 1 (Jul 2023)

• Lab descriptions updated

• Solutions created

• TerosHDL tool used

2022-06

BUT: Digital electronics 1 (Jun 2022)

Release notes:

• Text of all exercises is simplified and described in detail, suitable for self-study
• Assignments simplified for all labs
• New VHDL examples added
• Development environment added: TerosHDL

2021-07

BUT: Digital electronics 1 (Jul 2021)

Release notes:

• New board: Nexys A7 Artix- FPGA Trainer Board with XC7A50T-1CSG324C chip
• Development environment change: Vivado instead of ISE
• Usage of online tool EDA Playground
• New labs (Lab 2: Combinational logic, Lab 3: Introduction to Vivado, Lab 5: Latches and Flip-flops)
• Text of all labs extended by detailed descriptions, suitable for self-study
• Assignments added to all labs

2020-06

BUT: Digital electronics 1 (Jun 2020)