Brno Univ. of Technology, Jul 2024
- Repository renamed to
vhdl-course - Repository folder structure modified
- Challenges sections added to the labs
- Top level schematics redrawn
- List of labs modified
- Arithmetic circuit lab added
- FSM debouncer lab created
- Used Vivado VHDL templates
generatemechanism added- RTL and Gate level screenshots added
- Instructions for TerosHDL ver.5 created
- Comments and lab instructions updated
- Solutions updated and TerosHDL comments applied