Architecture

The internal view describes how the module implements its function. In VHDL, we can describe one or more architecture bodies with alternative implementations. The architecture body generally applies some operations to the values on input ports and generates values to be assigned to the output ports. Operations can be described either by processes that contain sequential statements operating on values, or by a set of components representing sub-circuits.

If the operation requires generation of intermediate values, these can be described using signals, analogous to the internal wires of a module. The syntax rule for architecture bodies shows the general outline:

architecture identifier of entity_name is
    signal signal_name : data_type;
    other signals...
begin
    concurrent statements...
end identifier;

An example of architecture body with two internal signals can is:

--------------------------------------------------
-- Architecture body for top level
--------------------------------------------------
architecture Behavioral of top_level is
    signal sig_product0 : std_logic;
    signal sig_product1 : std_logic;
begin
    -- Product terms
    sig_product0 <= not(a) and not(b);
    sig_product1 <= a and b;

    -- Sum of two product terms
    carry  <= sig_product0 or sig_product1;
end Behavioral;

Note, the main description between begin and end contains concurrent statements. Unlike a program in C language (where statements are executed sequentially), concurrent statements are like circuit parts that operate in parallel.