Merge remote-tracking branch 'origin/master' into ganesh_dev

ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml

@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.61e-9
+L2_SB_MUX_DELAY: 1.61e-9
+L4_SB_MUX_DELAY: 1.61e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 0.86e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.14e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+REGIN_TO_FF0_DELAY: 0.58e-9
+FF0_TO_FF1_DELAY: 0.56e-9

ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml

@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 2.31e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+LUT4_DELAY: 2.6e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9

ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml

@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 0.92e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.21e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9

DOC/requirements.txt

@@ -9,6 +9,12 @@
 sphinxcontrib-bibtex<2.0.0
 sphinxcontrib-tikz
 
+# Package required to embed youtube video
+sphinxcontrib-yt
+
+# Package required to convert SVG for latex building
+sphinxcontrib-svg2pdfconverter
+
 #Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
 #See:
 #  * https://github.com/sphinx-doc/sphinx/issues/3951

DOC/source/datasheet/qlsofa_hd/index.rst

@@ -14,3 +14,5 @@ QLSOFA HD
    qlsofa_hd_clb_arch
 
    qlsofa_hd_circuit_design
+
+   qlsofa_hd_timing

DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst

@@ -8,7 +8,7 @@ Architecture
 Floorplan
 ^^^^^^^^^
 
-QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
+QLSOFA HD FPGA share the same floorplan as SOFA HD FPGA.
 See details at :ref:`sofa_hd_fpga_arch_floorplan`.
 
 Tiles
@@ -46,6 +46,32 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
   |      |          |  cells.                                      |
   +------+----------+----------------------------------------------+
 
+.. _qlsofa_hd_fpga_arch_routing_arch:
+
+Routing Architecture
+^^^^^^^^^^^^^^^^^^^^
+
+The routing architecture shares the same principle as the SOFA HD routing architecture (See details in :ref:`sofa_hd_fpga_arch_routing_arch`).
+
+.. note:: Different from SOFA HD, each routing channel consists of 60 routing tracks. See details in :numref:`table_qlsofa_hd_fpga_arch_routing_track_distribution`.
+
+.. _table_qlsofa_hd_fpga_arch_routing_track_distribution:
+
+.. table:: Routing track distribution of QLSOFA HD FPGA 
+
+  +------------+------------------------------+
+  | Track type | Number of tracks per channel |
+  +============+==============================+
+  | Length-1   | 6  (10%)                     |
+  +------------+------------------------------+
+  | Length-2   | 6  (10%)                     |
+  +------------+------------------------------+
+  | Length-4   | 48 (80%)                     |
+  +------------+------------------------------+
+  | Total      | 60                           |
+  +------------+------------------------------+
+
+
 .. _qlsofa_hd_fpga_arch_scan_chain:
 
 Scan-chain

DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst

@@ -0,0 +1,100 @@
+.. _qlsofa_hd_timing:
+
+Timing Annotation
+-----------------
+
+.. _qlsofa_hd_timing_clb:
+
+Configurable Logic Block
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
+
+.. _fig_qlsofa_hd_fle_arch_timing:
+
+.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg
+  :width: 80%
+  :alt: Schematic of a logic element used in QLSOFA HD FPGA
+
+  Schematic of a logic element used in QLSOFA HD FPGA
+
+.. _table_qlsofa_hd_fle_arch_timing:
+
+.. table:: Path delays of logic element in the QLSOFA HD FPGA
+
+  +-------------------------+------------------------------+
+  | Path / Delay            | TT (unit: ns)                |
+  +=========================+==============================+
+  | in0 -> LUT3_out[0]      | 0.85                         |
+  +-------------------------+------------------------------+
+  | in1 -> LUT3_out[0]      | 0.57                         |
+  +-------------------------+------------------------------+
+  | in2 -> B                | 0.60                         |
+  +-------------------------+------------------------------+
+  |   B -> LUT3_out[0]      | 0.32                         |
+  +-------------------------+------------------------------+
+  | in0 -> LUT3_out[1]      | 0.90                         |
+  +-------------------------+------------------------------+
+  | in1 -> LUT3_out[1]      | 0.62                         |
+  +-------------------------+------------------------------+
+  |   B -> LUT3_out[1]      | 0.33                         |
+  +-------------------------+------------------------------+
+  | in0 -> LUT4_out         | 1.17                         |
+  +-------------------------+------------------------------+
+  | in1 -> LUT4_out         | 0.89                         |
+  +-------------------------+------------------------------+
+  | in2 -> LUT4_out         | 1.21                         |
+  +-------------------------+------------------------------+
+  | in3 -> LUT4_out         | 0.79                         |
+  +-------------------------+------------------------------+
+  | LUT3_out[0] -> A        | 0.56                         |
+  +-------------------------+------------------------------+
+  | LUT4_out[0] -> A        | 0.58                         |
+  +-------------------------+------------------------------+
+  | A -> out[0]             | 0.88                         |
+  +-------------------------+------------------------------+
+  | A -> FF[0]              | 0.56                         |
+  +-------------------------+------------------------------+
+  | FF[0] -> out[0]         | 0.88                         |
+  +-------------------------+------------------------------+
+  | LUT3_out[1] -> out[1]   | 0.89                         |
+  +-------------------------+------------------------------+
+  | LUT3_out[1] -> FF[1]    | 0.56                         |
+  +-------------------------+------------------------------+
+  | FF[1] -> out[1]         | 0.89                         |
+  +-------------------------+------------------------------+
+  | regin -> FF[0]          | 0.58                         |
+  +-------------------------+------------------------------+
+  | FF[0] -> FF[1]          | 0.56                         |
+  +-------------------------+------------------------------+
+
+.. _qlsofa_hd_timing_io:
+
+I/O Block
+^^^^^^^^^
+
+The path delays of I/O blocks in QLSOFA HD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`. 
+
+.. _qlsofa_hd_timing_routing:
+
+Routing Architecture
+^^^^^^^^^^^^^^^^^^^^
+
+The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_qlsofa_hd_routing_arch_timing`.
+
+.. _table_qlsofa_hd_routing_arch_timing:
+
+.. table:: Path delays of routing blocks in the QLSOFA HD FPGA
+
+  +---------------------------+------------------------------+
+  | Path / Delay              | TT (unit: ns)                |
+  +===========================+==============================+
+  | A -> B                    | 1.44                         |
+  +---------------------------+------------------------------+
+  | A -> C                    | 1.44                         |
+  +---------------------------+------------------------------+
+  | A -> D                    | 1.44                         |
+  +---------------------------+------------------------------+
+  | B -> E                    | 1.38                         |
+  +---------------------------+------------------------------+
+